PPCBranchCoalescing: Fix invalid branch weights (llvm#67211)

Re-normalize branch-weights after removing a block successor to avoid
branch-weights not adding up to 100%. This changes MIR for the
`test/CodeGen/PowerPC/branch_coalesce.ll` test like this:

```diff
-  successors: %bb.6(0x40000000); %bb.6(50.00%)
+  successors: %bb.6(0x80000000); %bb.6(100.00%)
```

This doesn't affect codegen on its own but fixing this helps with
fluctuations I have with some of my upcoming changes.

Author: MatzeB

llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp

@@ -702,6 +702,7 @@ bool PPCBranchCoalescing::mergeCandidates(CoalescingCandidateInfo &SourceRegion,
   TargetRegion.FallThroughBlock->transferSuccessorsAndUpdatePHIs(
       SourceRegion.FallThroughBlock);
   TargetRegion.FallThroughBlock->removeSuccessor(SourceRegion.BranchBlock);
+  TargetRegion.FallThroughBlock->normalizeSuccProbs();
 
   // Remove the blocks from the function.
   assert(SourceRegion.BranchBlock->empty() &&

llvm/test/CodeGen/PowerPC/branch_coalescing.mir

@@ -0,0 +1,104 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
+# RUN: llc -o - %s -run-pass=ppc-branch-coalescing | FileCheck %s
+--- |
+  target triple = "powerpc64le-unknown-linux-gnu"
+
+  define double @testBranchCoal(double %a, double %b, double %c, i32 %x) {
+    unreachable
+  }
+...
+---
+name:            testBranchCoal
+alignment:       16
+tracksRegLiveness: true
+liveins:
+  - { reg: '$f1', virtual-reg: '%0' }
+  - { reg: '$f2', virtual-reg: '%1' }
+  - { reg: '$f3', virtual-reg: '%2' }
+  - { reg: '$x6', virtual-reg: '%3' }
+frameInfo:
+  maxAlignment:    1
+constants:
+  - id:              0
+    value:           double 2.000000e-03
+    alignment:       8
+  - id:              1
+    value:           double 5.000000e-03
+    alignment:       8
+machineFunctionInfo: {}
+body:             |
+  ; CHECK-LABEL: name: testBranchCoal
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.1(0x1c71c71d), %bb.6(0x638e38e3)
+  ; CHECK-NEXT:   liveins: $f1, $f2, $f3, $x2, $x6
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:g8rc = COPY $x6
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:f8rc = COPY $f3
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:f8rc = COPY $f2
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:f8rc = COPY $f1
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:gprc = COPY [[COPY]].sub_32
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x2
+  ; CHECK-NEXT:   [[CMPLWI:%[0-9]+]]:crrc = CMPLWI killed [[COPY4]], 0
+  ; CHECK-NEXT:   [[ADDIStocHA8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDIStocHA8 [[COPY5]], %const.0
+  ; CHECK-NEXT:   [[LFD:%[0-9]+]]:f8rc = LFD target-flags(ppc-toc-lo) %const.0, killed [[ADDIStocHA8_]] :: (load (s64) from constant-pool)
+  ; CHECK-NEXT:   [[XXLXORdpz:%[0-9]+]]:f8rc = XXLXORdpz
+  ; CHECK-NEXT:   [[ADDIStocHA8_1:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDIStocHA8 [[COPY5]], %const.1
+  ; CHECK-NEXT:   [[LFD1:%[0-9]+]]:f8rc = LFD target-flags(ppc-toc-lo) %const.1, killed [[ADDIStocHA8_1]] :: (load (s64) from constant-pool)
+  ; CHECK-NEXT:   BCC 76, [[CMPLWI]], %bb.6
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   successors: %bb.6(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.6:
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:f8rc = PHI [[LFD]], %bb.1, [[COPY3]], %bb.0
+  ; CHECK-NEXT:   [[PHI1:%[0-9]+]]:f8rc = PHI [[XXLXORdpz]], %bb.1, [[COPY2]], %bb.0
+  ; CHECK-NEXT:   [[PHI2:%[0-9]+]]:f8rc = PHI [[LFD1]], %bb.1, [[COPY1]], %bb.0
+  ; CHECK-NEXT:   [[XSADDDP:%[0-9]+]]:vsfrc = nofpexcept XSADDDP killed [[PHI]], killed [[PHI1]], implicit $rm
+  ; CHECK-NEXT:   [[XSADDDP1:%[0-9]+]]:vsfrc = nofpexcept XSADDDP killed [[XSADDDP]], killed [[PHI2]], implicit $rm
+  ; CHECK-NEXT:   $f1 = COPY [[XSADDDP1]]
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm, implicit $f1
+  bb.0:
+    successors: %bb.1, %bb.2
+    liveins: $f1, $f2, $f3, $x2, $x6
+
+    %3:g8rc = COPY $x6
+    %2:f8rc = COPY $f3
+    %1:f8rc = COPY $f2
+    %0:f8rc = COPY $f1
+    %4:gprc = COPY %3.sub_32
+    %16:g8rc_and_g8rc_nox0 = COPY $x2
+    %5:crrc = CMPLWI killed %4, 0
+    %6:g8rc_and_g8rc_nox0 = ADDIStocHA8 %16, %const.0
+    %7:f8rc = LFD target-flags(ppc-toc-lo) %const.0, killed %6 :: (load (s64) from constant-pool)
+    BCC 76, %5, %bb.2
+
+  bb.1:
+
+  bb.2:
+    successors: %bb.3, %bb.4
+
+    %8:f8rc = PHI %7, %bb.1, %0, %bb.0
+    %9:f8rc = XXLXORdpz
+    BCC 76, %5, %bb.4
+
+  bb.3:
+
+  bb.4:
+    successors: %bb.5, %bb.6
+
+    %10:f8rc = PHI %9, %bb.3, %1, %bb.2
+    %11:g8rc_and_g8rc_nox0 = ADDIStocHA8 %16, %const.1
+    %12:f8rc = LFD target-flags(ppc-toc-lo) %const.1, killed %11 :: (load (s64) from constant-pool)
+    BCC 76, %5, %bb.6
+
+  bb.5:
+
+  bb.6:
+    %13:f8rc = PHI %12, %bb.5, %2, %bb.4
+    %14:vsfrc = nofpexcept XSADDDP killed %8, killed %10, implicit $rm
+    %15:vsfrc = nofpexcept XSADDDP killed %14, killed %13, implicit $rm
+    $f1 = COPY %15
+    BLR8 implicit $lr8, implicit $rm, implicit $f1
+
+...