Skip to content

Commit db02476

Browse files
arsenmarsenm
authored
AMDGPU: Fix not diagnosing unaligned VGPRs for vsrc operands (llvm#155104)
This was not checking the alignment requirement for 64-bit operands which accept inline immediates. Not all custom operand types were handled in the switch, so round out with explicit handling of all enum values, and change the default to use the default checks for unhandled cases. Fixes llvm#155095
1 parent 0263c15 commit db02476

File tree

3 files changed

+72
-11
lines changed

3 files changed

+72
-11
lines changed

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp‎

Lines changed: 32 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -4933,23 +4933,40 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
49334933

49344934
int RegClass = Desc.operands()[i].RegClass;
49354935

4936-
switch (Desc.operands()[i].OperandType) {
4936+
const MCOperandInfo &OpInfo = Desc.operands()[i];
4937+
switch (OpInfo.OperandType) {
49374938
case MCOI::OPERAND_REGISTER:
49384939
if (MI.getOperand(i).isImm() || MI.getOperand(i).isGlobal()) {
49394940
ErrInfo = "Illegal immediate value for operand.";
49404941
return false;
49414942
}
49424943
break;
49434944
case AMDGPU::OPERAND_REG_IMM_INT32:
4945+
case AMDGPU::OPERAND_REG_IMM_INT64:
4946+
case AMDGPU::OPERAND_REG_IMM_INT16:
49444947
case AMDGPU::OPERAND_REG_IMM_FP32:
49454948
case AMDGPU::OPERAND_REG_IMM_V2FP32:
4949+
case AMDGPU::OPERAND_REG_IMM_BF16:
4950+
case AMDGPU::OPERAND_REG_IMM_FP16:
4951+
case AMDGPU::OPERAND_REG_IMM_FP64:
4952+
case AMDGPU::OPERAND_REG_IMM_V2FP16:
4953+
case AMDGPU::OPERAND_REG_IMM_V2INT16:
4954+
case AMDGPU::OPERAND_REG_IMM_V2INT32:
4955+
case AMDGPU::OPERAND_REG_IMM_V2BF16:
49464956
break;
4957+
case AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16:
4958+
break;
4959+
break;
4960+
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
49474961
case AMDGPU::OPERAND_REG_INLINE_C_INT32:
4948-
case AMDGPU::OPERAND_REG_INLINE_C_FP32:
49494962
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
4963+
case AMDGPU::OPERAND_REG_INLINE_C_FP32:
49504964
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
4951-
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
4965+
case AMDGPU::OPERAND_REG_INLINE_C_BF16:
49524966
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
4967+
case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
4968+
case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:
4969+
case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
49534970
case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
49544971
case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
49554972
case AMDGPU::OPERAND_REG_INLINE_AC_FP64: {
@@ -4965,6 +4982,10 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
49654982
return false;
49664983
}
49674984
break;
4985+
case AMDGPU::OPERAND_INPUT_MODS:
4986+
case AMDGPU::OPERAND_SDWA_VOPC_DST:
4987+
case AMDGPU::OPERAND_KIMM16:
4988+
break;
49684989
case MCOI::OPERAND_IMMEDIATE:
49694990
case AMDGPU::OPERAND_KIMM32:
49704991
case AMDGPU::OPERAND_KIMM64:
@@ -4976,9 +4997,15 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
49764997
ErrInfo = "Expected immediate, but got non-immediate";
49774998
return false;
49784999
}
4979-
[[fallthrough]];
5000+
break;
5001+
case MCOI::OPERAND_UNKNOWN:
5002+
case MCOI::OPERAND_MEMORY:
5003+
case MCOI::OPERAND_PCREL:
5004+
break;
49805005
default:
4981-
continue;
5006+
if (OpInfo.isGenericType())
5007+
continue;
5008+
break;
49825009
}
49835010

49845011
if (!MO.isReg())

‎llvm/test/CodeGen/AMDGPU/remat-vop.mir‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -278,16 +278,16 @@ machineFunctionInfo:
278278
body: |
279279
bb.0:
280280
; GCN-LABEL: name: test_remat_v_cvt_i32_f64_e64_undef
281-
; GCN: [[V_CVT_I32_F64_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e64 0, undef %1:vreg_64, 0, 0, implicit $exec, implicit $mode
282-
; GCN-NEXT: [[V_CVT_I32_F64_e64_1:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e64 0, undef %1:vreg_64, 0, 0, implicit $exec, implicit $mode
283-
; GCN-NEXT: [[V_CVT_I32_F64_e64_2:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e64 0, undef %1:vreg_64, 0, 0, implicit $exec, implicit $mode
281+
; GCN: [[V_CVT_I32_F64_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e64 0, undef %1:vreg_64_align2, 0, 0, implicit $exec, implicit $mode
282+
; GCN-NEXT: [[V_CVT_I32_F64_e64_1:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e64 0, undef %1:vreg_64_align2, 0, 0, implicit $exec, implicit $mode
283+
; GCN-NEXT: [[V_CVT_I32_F64_e64_2:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e64 0, undef %1:vreg_64_align2, 0, 0, implicit $exec, implicit $mode
284284
; GCN-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e64_]]
285285
; GCN-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e64_1]]
286286
; GCN-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e64_2]]
287287
; GCN-NEXT: S_ENDPGM 0
288-
%1:vgpr_32 = nofpexcept V_CVT_I32_F64_e64 0, undef %0:vreg_64, 0, 0, implicit $exec, implicit $mode
289-
%2:vgpr_32 = nofpexcept V_CVT_I32_F64_e64 0, undef %0:vreg_64, 0, 0, implicit $exec, implicit $mode
290-
%3:vgpr_32 = nofpexcept V_CVT_I32_F64_e64 0, undef %0:vreg_64, 0, 0, implicit $exec, implicit $mode
288+
%1:vgpr_32 = nofpexcept V_CVT_I32_F64_e64 0, undef %0:vreg_64_align2, 0, 0, implicit $exec, implicit $mode
289+
%2:vgpr_32 = nofpexcept V_CVT_I32_F64_e64 0, undef %0:vreg_64_align2, 0, 0, implicit $exec, implicit $mode
290+
%3:vgpr_32 = nofpexcept V_CVT_I32_F64_e64 0, undef %0:vreg_64_align2, 0, 0, implicit $exec, implicit $mode
291291
S_NOP 0, implicit %1
292292
S_NOP 0, implicit %2
293293
S_NOP 0, implicit %3

‎llvm/test/MachineVerifier/AMDGPU/unsupported-unaligned-vgpr-check-vsrc-operand.mir‎

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,34 @@
1+
# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -run-pass=none -filetype=null %s 2>&1 | FileCheck -implicit-check-not="Bad machine code" %s
2+
3+
# 64-bit vsrc operands were not correctly diagnosed with unaligned registers.
4+
5+
---
6+
name: uses_unaligned_physreg
7+
tracksRegLiveness: true
8+
body: |
9+
bb.0:
10+
liveins: $vgpr1_vgpr2
11+
12+
; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
13+
; CHECK: - instruction: $vcc = V_CMP_NE_U64_e64 0, $vgpr1_vgpr2, implicit $exec
14+
15+
$vcc = V_CMP_NE_U64_e64 0, $vgpr1_vgpr2, implicit $exec
16+
17+
; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
18+
; CHECK: *** Bad machine code: Illegal physical register for instruction ***
19+
; CHECK: - instruction: V_CMP_NE_U64_e32 0, $vgpr1_vgpr2, implicit-def $vcc, implicit $exec
20+
V_CMP_NE_U64_e32 0, $vgpr1_vgpr2, implicit-def $vcc, implicit $exec
21+
22+
%0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
23+
%1:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
24+
%2:vreg_64 = IMPLICIT_DEF
25+
26+
; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
27+
; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
28+
%3:areg_128_align2 = V_MFMA_F32_4X4X1F32_e64 %0, %1, %2, 0, 0, 0, implicit $mode, implicit $exec
29+
%4:vreg_64 = IMPLICIT_DEF
30+
31+
; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
32+
; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
33+
%5:vreg_128_align2 = V_MFMA_F32_4X4X1F32_vgprcd_e64 %0, %1, %4, 0, 0, 0, implicit $mode, implicit $exec
34+
...

0 commit comments

Comments
 (0)