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Address review comment
1 parent 8e8897b commit f7a5a33

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cpp/ql/lib/experimental/semmle/code/cpp/ir/dataflow/internal/DataFlowImpl.qll

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@@ -693,6 +693,7 @@ private module Stage1 implements StageSig {
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(
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cc = false
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or
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cc = true and
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not reducedViableImplInCallContext(call, _, _)
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)
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or

cpp/ql/lib/experimental/semmle/code/cpp/ir/dataflow/internal/DataFlowImpl2.qll

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@@ -693,6 +693,7 @@ private module Stage1 implements StageSig {
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(
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cc = false
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or
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cc = true and
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not reducedViableImplInCallContext(call, _, _)
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)
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or

cpp/ql/lib/experimental/semmle/code/cpp/ir/dataflow/internal/DataFlowImpl3.qll

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@@ -693,6 +693,7 @@ private module Stage1 implements StageSig {
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(
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cc = false
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or
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cc = true and
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not reducedViableImplInCallContext(call, _, _)
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)
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or

cpp/ql/lib/experimental/semmle/code/cpp/ir/dataflow/internal/DataFlowImpl4.qll

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@@ -693,6 +693,7 @@ private module Stage1 implements StageSig {
693693
(
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cc = false
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or
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cc = true and
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not reducedViableImplInCallContext(call, _, _)
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)
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or

cpp/ql/lib/semmle/code/cpp/dataflow/internal/DataFlowImpl.qll

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Original file line numberDiff line numberDiff line change
@@ -693,6 +693,7 @@ private module Stage1 implements StageSig {
693693
(
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cc = false
695695
or
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cc = true and
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not reducedViableImplInCallContext(call, _, _)
697698
)
698699
or

cpp/ql/lib/semmle/code/cpp/dataflow/internal/DataFlowImpl2.qll

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Original file line numberDiff line numberDiff line change
@@ -693,6 +693,7 @@ private module Stage1 implements StageSig {
693693
(
694694
cc = false
695695
or
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cc = true and
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not reducedViableImplInCallContext(call, _, _)
697698
)
698699
or

cpp/ql/lib/semmle/code/cpp/dataflow/internal/DataFlowImpl3.qll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -693,6 +693,7 @@ private module Stage1 implements StageSig {
693693
(
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cc = false
695695
or
696+
cc = true and
696697
not reducedViableImplInCallContext(call, _, _)
697698
)
698699
or

cpp/ql/lib/semmle/code/cpp/dataflow/internal/DataFlowImpl4.qll

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Original file line numberDiff line numberDiff line change
@@ -693,6 +693,7 @@ private module Stage1 implements StageSig {
693693
(
694694
cc = false
695695
or
696+
cc = true and
696697
not reducedViableImplInCallContext(call, _, _)
697698
)
698699
or

cpp/ql/lib/semmle/code/cpp/dataflow/internal/DataFlowImplLocal.qll

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@@ -693,6 +693,7 @@ private module Stage1 implements StageSig {
693693
(
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cc = false
695695
or
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cc = true and
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not reducedViableImplInCallContext(call, _, _)
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)
698699
or

cpp/ql/lib/semmle/code/cpp/ir/dataflow/internal/DataFlowImpl.qll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -693,6 +693,7 @@ private module Stage1 implements StageSig {
693693
(
694694
cc = false
695695
or
696+
cc = true and
696697
not reducedViableImplInCallContext(call, _, _)
697698
)
698699
or

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