Merge branch 'release/rocm-rel-6.4' into zichguan/cherrypick-cstdint-fix

Author: jharryma

clang/include/clang/Driver/Options.td

@@ -4457,8 +4457,8 @@ def gheterogeneous_dwarf_EQ : Joined<["-"], "gheterogeneous-dwarf=">,
   MarshallingInfoEnum<CodeGenOpts<"HeterogeneousDwarfMode">, "Disabled">;
 def gheterogeneous_dwarf : Flag<["-"], "gheterogeneous-dwarf">, Group<g_Group>,
   Visibility<[ClangOption, CC1Option]>,
-  HelpText<"Enable DIExpr-based DWARF extensions for heterogeneous debugging">,
-  Alias<gheterogeneous_dwarf_EQ>, AliasArgs<["diexpr"]>;
+  HelpText<"Enable DIExpression-based DWARF extensions for heterogeneous debugging">,
+  Alias<gheterogeneous_dwarf_EQ>, AliasArgs<["diexpression"]>;
 def gno_heterogeneous_dwarf : Flag<["-"], "gno-heterogeneous-dwarf">,
   Visibility<[ClangOption, CC1Option]>,
   Group<g_Group>,

clang/lib/Driver/ToolChains/Clang.cpp

@@ -4840,11 +4840,12 @@ renderDebugOptions(const ToolChain &TC, const Driver &D, const llvm::Triple &T,
     assert(Aliased.isValid() && "gheterogeneous-dwarf must be an alias");
     assert(Aliased.getName() == "gheterogeneous-dwarf=" &&
            "gheterogeneous-dwarf must alias gheterogeneous-dwarf=");
-    assert(StringRef(GHeterogeneousDwarf.getAliasArgs()) == "diexpr" &&
-           GHeterogeneousDwarf.getAliasArgs()[strlen("diexpr") + 1] == '\0' &&
-           "gheterogeneous-dwarf must alias gheterogeneous-dwarf=diexpr");
+    assert(StringRef(GHeterogeneousDwarf.getAliasArgs()) == "diexpression" &&
+           GHeterogeneousDwarf.getAliasArgs()[strlen("diexpression") + 1] ==
+               '\0' &&
+           "gheterogeneous-dwarf must alias gheterogeneous-dwarf=diexpression");
 #endif
-    CmdArgs.push_back("-gheterogeneous-dwarf=diexpr");
+    CmdArgs.push_back("-gheterogeneous-dwarf=diexpression");
   }
 
   // This controls whether or not we perform JustMyCode instrumentation.

clang/test/CodeGenHIP/debug-info-cc1-option.hip

@@ -5,8 +5,7 @@
 // and aliases the new default. This is needed for transitioning flang-legacy
 // as it depends on the -cc1 interface.
 
-// CHECK: call void @llvm.dbg.def
-// CHECK: !DIExpr(
+// CHECK: #dbg_declare{{.*}}DIExpression{{.*}}DIOp
 __attribute__((device)) void kernel1(int Arg) {
   int FuncVar;
 }

clang/test/Driver/amdgpu-debug.cl

@@ -7,7 +7,7 @@
 // CHECK-SIMPLE-NOT: "-disable-O0-optnone"
 // CHECK-SIMPLE-NOT: "-debug-info-kind=line-tables-only"
 // CHECK-SIMPLE-DAG: "-mllvm" "-amdgpu-spill-cfi-saved-regs"
-// CHECK-SIMPLE-DAG: "-gheterogeneous-dwarf=diexpr"
+// CHECK-SIMPLE-DAG: "-gheterogeneous-dwarf=diexpression"
 // CHECK-SIMPLE-DAG: "-debugger-tuning=gdb"
 // CHECK-SIMPLE-NOT: "-disable-O0-optnone"
 // CHECK-SIMPLE-NOT: "-debug-info-kind=line-tables-only"
@@ -21,7 +21,7 @@
 // Check that -gheterogeneous-dwarf can be enabled for non-AMDGCN
 // RUN: %clang -### -target x86_64-linux-gnu -x cl -c -nogpuinc -nogpulib  -emit-llvm -gheterogeneous-dwarf %s 2>&1 | FileCheck -check-prefix=CHECK-EXPLICIT-HETEROGENEOUS %s
 // CHECK-EXPLICIT-HETEROGENEOUS: "-cc1"
-// CHECK-EXPLICIT-HETEROGENEOUS: "-gheterogeneous-dwarf=diexpr"
+// CHECK-EXPLICIT-HETEROGENEOUS: "-gheterogeneous-dwarf=diexpression"
 
 // Check that -gheterogeneous-dwarf can be disabled for AMDGCN
 // RUN: %clang -### -target amdgcn-amd-amdhsa -x cl -c -nogpuinc -nogpulib  -emit-llvm -g -gno-heterogeneous-dwarf %s 2>&1 | FileCheck -check-prefix=CHECK-NO-HETEROGENEOUS %s

llvm/include/llvm/CodeGen/MachineFunction.h

@@ -592,6 +592,8 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
   void substituteDebugValuesForInst(const MachineInstr &Old, MachineInstr &New,
                                     unsigned MaxOperand = UINT_MAX);
 
+  using SalvageCopySSAResult = std::pair<DebugInstrOperandPair, MachineInstr *>;
+
   /// Find the underlying  defining instruction / operand for a COPY instruction
   /// while in SSA form. Copies do not actually define values -- they move them
   /// between registers. Labelling a COPY-like instruction with an instruction
@@ -603,11 +605,11 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
   /// \p MI The copy-like instruction to salvage.
   /// \p DbgPHICache A container to cache already-solved COPYs.
   /// \returns An instruction/operand pair identifying the defining value.
-  DebugInstrOperandPair
+  SalvageCopySSAResult
   salvageCopySSA(MachineInstr &MI,
-                 DenseMap<Register, DebugInstrOperandPair> &DbgPHICache);
+                 DenseMap<Register, SalvageCopySSAResult> &DbgPHICache);
 
-  DebugInstrOperandPair salvageCopySSAImpl(MachineInstr &MI);
+  SalvageCopySSAResult salvageCopySSAImpl(MachineInstr &MI);
 
   /// Finalise any partially emitted debug instructions. These are DBG_INSTR_REF
   /// instructions where we only knew the vreg of the value they use, not the

llvm/include/llvm/CodeGen/TargetSchedule.h

@@ -45,6 +45,16 @@ class TargetSchedModel {
 
   unsigned computeInstrLatency(const MCSchedClassDesc &SCDesc) const;
 
+  // EnableSchedModel and EnableSchedItins are used to control whether or not to
+  // use the Target's {SchedMachineModel, InstrItins} for hardware infor based
+  // Scheduling decisions. If both are enabled, as is the default, preference
+  // will be given to one based on the API implementation. By disabling one, we
+  // can force preference of the other. By disabling both, we will throw away
+  // any target specific hardware details for scheduling decisions, and fall
+  // into things that provide generic info such as defaultDefLatency.
+  bool EnableSchedModel = true;
+  bool EnableSchedItins = true;
+
 public:
   TargetSchedModel() : SchedModel(MCSchedModel::Default) {}
 
@@ -53,7 +63,8 @@ class TargetSchedModel {
   /// The machine model API keeps a copy of the top-level MCSchedModel table
   /// indices and may query TargetSubtargetInfo and TargetInstrInfo to resolve
   /// dynamic properties.
-  void init(const TargetSubtargetInfo *TSInfo);
+  void init(const TargetSubtargetInfo *TSInfo, bool EnableSModel = true,
+            bool EnableSItins = true);
 
   /// Return the MCSchedClassDesc for this instruction.
   const MCSchedClassDesc *resolveSchedClass(const MachineInstr *MI) const;

llvm/include/llvm/IR/DebugInfoMetadata.h

@@ -1098,6 +1098,12 @@ class DIDerivedType : public DIType {
 
   TempDIDerivedType clone() const { return cloneImpl(); }
 
+  TempDIDerivedType cloneWithAddressSpace(unsigned DWARFAddrSpace) const {
+    auto Tmp = clone();
+    Tmp->DWARFAddressSpace = DWARFAddrSpace;
+    return Tmp;
+  }
+
   /// Get the base type this is derived from.
   DIType *getBaseType() const { return cast_or_null<DIType>(getRawBaseType()); }
   Metadata *getRawBaseType() const { return getOperand(3); }
@@ -3345,6 +3351,19 @@ class DIExpression : public MDNode {
   element_iterator elements_begin() const { return getElements().begin(); }
   element_iterator elements_end() const { return getElements().end(); }
 
+  /// Returns the pointer address space this DIOp-based DIExpression produces.
+  /// Note that this may diverge from the the pointer address space of the
+  /// result type. When there is a divergent address space, the DIExpression
+  /// must produce a generic pointer whose value can be proven to belong to a
+  /// more specific address space. For instance in this expression, this
+  /// function returns 4:
+  ///
+  ///   !DIExpression(DIOpArg(0, ptr addrspace(4)), DIOpConvert(ptr))
+  ///
+  /// A divergent address space can be created by a DIOpConvert, and is
+  /// preserved across DIOpReinterpret.
+  std::optional<unsigned> getNewDivergentAddrSpace() const;
+
   /// A lightweight wrapper around an expression operand.
   ///
   /// TODO: Store arguments directly and change \a DIExpression to store a

llvm/include/llvm/Transforms/Utils/Local.h

@@ -356,7 +356,7 @@ Value *salvageDebugInfoImpl(Instruction &I, uint64_t CurrentLocOps,
 /// introducing a use-before-def, it is either salvaged (\ref salvageDebugInfo)
 /// or deleted. Returns true if any debug users were updated.
 bool replaceAllDbgUsesWith(Instruction &From, Value &To, Instruction &DomPoint,
-                           DominatorTree &DT);
+                           const DominatorTree &DT);
 
 /// If a terminator in an unreachable basic block has an operand of type
 /// Instruction, transform it into poison. Return true if any operands

llvm/lib/CodeGen/AsmPrinter/DebugLocStream.cpp

@@ -40,5 +40,5 @@ void DebugLocStream::finalizeEntry() {
 DebugLocStream::ListBuilder::~ListBuilder() {
   if (!Locs.finalizeList(Asm))
     return;
-  V.emplace<Loc::Multi>(ListIndex, TagOffset);
+  V.emplace<Loc::Multi>(ListIndex, TagOffset, CommonAddrSpace);
 }

llvm/lib/CodeGen/AsmPrinter/DebugLocStream.h

@@ -157,6 +157,7 @@ class DebugLocStream::ListBuilder {
   DbgVariable &V;
   size_t ListIndex;
   std::optional<uint8_t> TagOffset;
+  std::optional<unsigned> CommonAddrSpace;
 
 public:
   ListBuilder(DebugLocStream &Locs, DwarfCompileUnit &CU, AsmPrinter &Asm,
@@ -168,6 +169,11 @@ class DebugLocStream::ListBuilder {
     TagOffset = TO;
   }
 
+  void setCommonDivergentAddrSpace(unsigned AS) { CommonAddrSpace = AS; }
+  bool hasCommonDivergentAddrSpace() const {
+    return CommonAddrSpace != std::nullopt;
+  }
+
   /// Finalize the list.
   ///
   /// If the list is empty, delete it.  Otherwise, finalize it by creating a