[AMDGPU] Add SGPR class liverange split instructions into BB Prolog

The COPY inserted for liverange split during sgpr-regalloc pipeline
currently breaks the BB prolog during the subsequent vgpr-regalloc
phase while spilling and/or splitting the vector liveranges. This
patch fixes it by correctly including the necessary instructions
into the BB prolog.

Change-Id: Ic747d09771839f7371a44c85b606ea06e972427b

Author: cdevadas

llvm/include/llvm/CodeGen/MachineInstr.h

@@ -114,6 +114,7 @@ class MachineInstr
                              // this instruction.
     Unpredictable = 1 << 16, // Instruction with unpredictable condition.
     NoConvergent = 1 << 17,  // Call does not require convergence guarantees.
+    LRSplit = 1 << 18        // Live range split instruction.
   };
 
 private:

llvm/lib/CodeGen/SplitKit.cpp

@@ -554,6 +554,7 @@ SlotIndex SplitEditor::buildCopy(Register FromReg, Register ToReg,
     // The full vreg is copied.
     MachineInstr *CopyMI =
         BuildMI(MBB, InsertBefore, DebugLoc(), Desc, ToReg).addReg(FromReg);
+    CopyMI->setFlag(MachineInstr::LRSplit);
     return Indexes.insertMachineInstrInMaps(*CopyMI, Late).getRegSlot();
   }
 

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

@@ -8930,15 +8930,18 @@ bool SIInstrInfo::isBasicBlockPrologue(const MachineInstr &MI,
   // needed by the prolog. However, the insertions for scalar registers can
   // always be placed at the BB top as they are independent of the exec mask
   // value.
+  const MachineFunction *MF = MI.getParent()->getParent();
+  const MachineRegisterInfo &MRI = MF->getRegInfo();
   bool IsNullOrVectorRegister = true;
-  if (Reg) {
-    const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
+  if (Reg)
     IsNullOrVectorRegister = !RI.isSGPRClass(RI.getRegClassForReg(MRI, Reg));
-  }
 
   uint16_t Opcode = MI.getOpcode();
   return IsNullOrVectorRegister &&
          (isSGPRSpill(Opcode) || isWWMRegSpillOpcode(Opcode) ||
+          (MI.getFlag(MachineInstr::LRSplit) &&
+           RI.isSGPRClass(
+               RI.getRegClassForReg(MRI, MI.getOperand(0).getReg()))) ||
           (!MI.isTerminator() && Opcode != AMDGPU::COPY &&
            MI.modifiesRegister(AMDGPU::EXEC, &RI)));
 }