dts: add support for Atmel SAM Timer Counter (TC)

Add support for Timer Counter (TC) on SAM E70/V71 series.

Signed-off-by: Piotr Mienkowski <[email protected]>

Author: mnkp

dts/arm/atmel/same70-pinctrl.dtsi

@@ -108,6 +108,42 @@
 			DT_ATMEL_PIN(usart2, rxd2, d, 15, b);
 			DT_ATMEL_PIN(usart2, sck2, d, 17, b);
 			DT_ATMEL_PIN(usart2, txd2, d, 16, b);
+			DT_ATMEL_PIN(tc0, tclk0, a, 4, b);
+			DT_ATMEL_PIN(tc0, tclk1, a, 28, b);
+			DT_ATMEL_PIN(tc0, tclk2, a, 29, b);
+			DT_ATMEL_PIN(tc0, tioa0, a, 0, b);
+			DT_ATMEL_PIN(tc0, tioa1, a, 15, b);
+			DT_ATMEL_PIN(tc0, tioa2, a, 26, b);
+			DT_ATMEL_PIN(tc0, tiob0, a, 1, b);
+			DT_ATMEL_PIN(tc0, tiob1, a, 16, b);
+			DT_ATMEL_PIN(tc0, tiob2, a, 27, b);
+			DT_ATMEL_PIN(tc1, tclk3, c, 25, b);
+			DT_ATMEL_PIN(tc1, tclk4, c, 28, b);
+			DT_ATMEL_PIN(tc1, tclk5, c, 31, b);
+			DT_ATMEL_PIN(tc1, tioa3, c, 23, b);
+			DT_ATMEL_PIN(tc1, tioa4, c, 26, b);
+			DT_ATMEL_PIN(tc1, tioa5, c, 29, b);
+			DT_ATMEL_PIN(tc1, tiob3, c, 24, b);
+			DT_ATMEL_PIN(tc1, tiob4, c, 27, b);
+			DT_ATMEL_PIN(tc1, tiob5, c, 30, b);
+			DT_ATMEL_PIN(tc2, tclk6, c, 7, b);
+			DT_ATMEL_PIN(tc2, tclk7, c, 10, b);
+			DT_ATMEL_PIN(tc2, tclk8, c, 14, b);
+			DT_ATMEL_PIN(tc2, tioa6, c, 5, b);
+			DT_ATMEL_PIN(tc2, tioa7, c, 8, b);
+			DT_ATMEL_PIN(tc2, tioa8, c, 11, b);
+			DT_ATMEL_PIN(tc2, tiob6, c, 6, b);
+			DT_ATMEL_PIN(tc2, tiob7, c, 9, b);
+			DT_ATMEL_PIN(tc2, tiob8, c, 12, b);
+			DT_ATMEL_PIN(tc3, tclk9, e, 2, b);
+			DT_ATMEL_PIN(tc3, tclk10, e, 5, b);
+			DT_ATMEL_PIN(tc3, tclk11, d, 24, c);
+			DT_ATMEL_PIN(tc3, tioa9, e, 0, b);
+			DT_ATMEL_PIN(tc3, tioa10, e, 3, b);
+			DT_ATMEL_PIN(tc3, tioa11, d, 21, c);
+			DT_ATMEL_PIN(tc3, tiob9, e, 1, b);
+			DT_ATMEL_PIN(tc3, tiob10, e, 4, b);
+			DT_ATMEL_PIN(tc3, tiob11, d, 22, c);
 		};
 	};
 };

dts/arm/atmel/same70.dtsi

@@ -355,6 +355,50 @@
 				     &pd8a_gmac_gmdc &pd9a_gmac_gmdio>;
 		};
 
+		tc0: tc@4000C000 {
+			compatible = "atmel,sam-tc";
+			reg = <0x4000C000 0x100>;
+			interrupts = <23 0
+				      24 0
+				      25 0>;
+			peripheral-id = <23 24 25>;
+			status = "disabled";
+			label = "TC0";
+		};
+
+		tc1: tc@40010000 {
+			compatible = "atmel,sam-tc";
+			reg = <0x40010000 0x100>;
+			interrupts = <26 0
+				      27 0
+				      28 0>;
+			peripheral-id = <26 27 28>;
+			status = "disabled";
+			label = "TC1";
+		};
+
+		tc2: tc@40014000 {
+			compatible = "atmel,sam-tc";
+			reg = <0x40014000 0x100>;
+			interrupts = <47 0
+				      48 0
+				      49 0>;
+			peripheral-id = <47 48 49>;
+			status = "disabled";
+			label = "TC2";
+		};
+
+		tc3: tc@40054000 {
+			compatible = "atmel,sam-tc";
+			reg = <0x40054000 0x100>;
+			interrupts = <50 0
+				      51 0
+				      52 0>;
+			peripheral-id = <50 51 52>;
+			status = "disabled";
+			label = "TC3";
+		};
+
 		trng: random@40070000 {
 			compatible = "atmel,sam-trng";
 			reg = <0x40070000 0x4000>;

dts/bindings/timer/atmel,sam-tc.yaml

@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM Timer Counter (TC) node
+
+compatible: "atmel,sam-tc"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
+
+    peripheral-id:
+      type: array
+      description: peripheral ID
+      required: true
+
+    pinctrl-0:
+      type: phandles
+      required: false
+      description: |
+        PIO pin configuration for Timer Counter signals.  We expect that
+        the phandles will reference pinctrl nodes.  These nodes will
+        have a nodelabel that matches the Atmel SoC HAL defines and
+        be of the form p<port><pin><periph>_<inst>_<signal>.
+
+        In Quadrature Decoder mode TIOA0 & TIOB0 signals are expected
+
+        For example the TC0 on SAME7x would be
+           pinctrl-0 = <&pa0b_tc0_tioa0 &pa1b_tc0_tiob0>;