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Reapply "[AMDGPU][MC] Allow op_sel in v_alignbit_b32 etc in GFX9 and GFX10 (llvm#142188)"
This reverts commit ba271cc.
1 parent ad6d5d2 commit 0ae8aaf

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12 files changed

+271
-12
lines changed

12 files changed

+271
-12
lines changed

‎llvm/lib/Target/AMDGPU/SIInstructions.td‎

Lines changed: 42 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2473,6 +2473,7 @@ def : AMDGPUPat <
24732473
>;
24742474

24752475
let True16Predicate = NotHasTrue16BitInsts in {
2476+
let SubtargetPredicate = isNotGFX9Plus in {
24762477
def : ROTRPattern <V_ALIGNBIT_B32_e64>;
24772478

24782479
def : GCNPat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))),
@@ -2482,6 +2483,35 @@ def : GCNPat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))),
24822483
def : GCNPat<(i32 (trunc (srl i64:$src0, (i32 ShiftAmt32Imm:$src1)))),
24832484
(V_ALIGNBIT_B32_e64 (i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
24842485
(i32 (EXTRACT_SUBREG (i64 $src0), sub0)), $src1)>;
2486+
} // isNotGFX9Plus
2487+
2488+
let SubtargetPredicate = isGFX9GFX10 in {
2489+
def : GCNPat <
2490+
(rotr i32:$src0, i32:$src1),
2491+
(V_ALIGNBIT_B32_opsel_e64 /* src0_modifiers */ 0, $src0,
2492+
/* src1_modifiers */ 0, $src0,
2493+
/* src2_modifiers */ 0,
2494+
$src1, /* clamp */ 0, /* op_sel */ 0)
2495+
>;
2496+
2497+
foreach pat = [(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))),
2498+
(i32 (trunc (srl i64:$src0, (i32 ShiftAmt32Imm:$src1))))] in
2499+
def : GCNPat<pat,
2500+
(V_ALIGNBIT_B32_opsel_e64 0, /* src0_modifiers */
2501+
(i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
2502+
0, /* src1_modifiers */
2503+
(i32 (EXTRACT_SUBREG (i64 $src0), sub0)),
2504+
0, /* src2_modifiers */
2505+
$src1, /* clamp */ 0, /* op_sel */ 0)
2506+
>;
2507+
2508+
def : GCNPat<(fshr i32:$src0, i32:$src1, i32:$src2),
2509+
(V_ALIGNBIT_B32_opsel_e64 /* src0_modifiers */ 0, $src0,
2510+
/* src1_modifiers */ 0, $src1,
2511+
/* src2_modifiers */ 0,
2512+
$src2, /* clamp */ 0, /* op_sel */ 0)
2513+
>;
2514+
} // isGFX9GFX10
24852515
} // end True16Predicate = NotHasTrue16BitInsts
24862516

24872517
let True16Predicate = UseRealTrue16Insts in {
@@ -3082,6 +3112,8 @@ def : GCNPat <
30823112
(i32 (EXTRACT_SUBREG $a, sub0))), (i32 1))
30833113
>;
30843114

3115+
// This pattern for bswap is used for pre-GFX8. For GFX8+, bswap is mapped
3116+
// to V_PERM_B32.
30853117
let True16Predicate = NotHasTrue16BitInsts in
30863118
def : GCNPat <
30873119
(i32 (bswap i32:$a)),
@@ -3557,15 +3589,20 @@ def : GCNPat <
35573589

35583590
// Take the upper 16 bits from V[0] and the lower 16 bits from V[1]
35593591
// Special case, can use V_ALIGNBIT (always uses encoded literal)
3560-
let True16Predicate = NotHasTrue16BitInsts in
3561-
def : GCNPat <
3592+
let True16Predicate = NotHasTrue16BitInsts in {
3593+
defvar BuildVectorToAlignBitPat =
35623594
(vecTy (DivergentBinFrag<build_vector>
35633595
(Ty !if(!eq(Ty, i16),
35643596
(Ty (trunc (srl VGPR_32:$a, (i32 16)))),
35653597
(Ty (bitconvert (i16 (trunc (srl VGPR_32:$a, (i32 16)))))))),
3566-
(Ty VGPR_32:$b))),
3567-
(V_ALIGNBIT_B32_e64 VGPR_32:$b, VGPR_32:$a, (i32 16))
3568-
>;
3598+
(Ty VGPR_32:$b)));
3599+
3600+
let SubtargetPredicate = isNotGFX9Plus in
3601+
def : GCNPat<BuildVectorToAlignBitPat, (V_ALIGNBIT_B32_e64 VGPR_32:$b, VGPR_32:$a, (i32 16))>;
3602+
3603+
let SubtargetPredicate = isGFX9GFX10 in
3604+
def : GCNPat<BuildVectorToAlignBitPat, (V_ALIGNBIT_B32_opsel_e64 0, VGPR_32:$b, 0, VGPR_32:$a, 0, (i32 16), 0, 0)>;
3605+
} //True16Predicate = NotHasTrue16BitInsts
35693606

35703607
let True16Predicate = UseFakeTrue16Insts in
35713608
def : GCNPat <

‎llvm/lib/Target/AMDGPU/VOP3Instructions.td‎

Lines changed: 37 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -224,6 +224,12 @@ defm V_ALIGNBIT_B32 : VOP3Inst_t16_with_profiles <"v_alignbit_b32",
224224
fshr, null_frag>;
225225

226226
defm V_ALIGNBYTE_B32 : VOP3Inst <"v_alignbyte_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbyte>;
227+
228+
// In gfx9 and 10, opsel is allowed for V_ALIGNBIT_B32 and V_ALIGNBYTE_B32.
229+
// Hardware uses opsel[1:0] to byte-select src2. Other opsel bits are ignored.
230+
defm V_ALIGNBIT_B32_opsel : VOP3Inst <"v_alignbit_b32_opsel", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_OPSEL>>;
231+
defm V_ALIGNBYTE_B32_opsel : VOP3Inst <"v_alignbyte_b32_opsel", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_OPSEL>>;
232+
227233
let True16Predicate = UseRealTrue16Insts in
228234
defm V_ALIGNBYTE_B32_t16 : VOP3Inst <"v_alignbyte_b32_t16", VOP3_Profile_True16<VOP_I32_I32_I32_I16, VOP3_OPSEL>>;
229235
let True16Predicate = UseFakeTrue16Insts in
@@ -265,6 +271,16 @@ let SchedRW = [WriteDoubleAdd], FPDPRounding = 1 in {
265271
} // End SchedRW = [WriteDoubleAdd], FPDPRounding = 1
266272
} // End isReMaterializable = 1
267273

274+
let SubtargetPredicate = isGFX9GFX10 in
275+
def : GCNPat <
276+
(i32 (int_amdgcn_alignbyte (i32 (VOP3OpSelMods i32:$src0, i32:$src0_modifiers)),
277+
(i32 (VOP3OpSelMods i32:$src1, i32:$src1_modifiers)),
278+
(i32 (VOP3OpSelMods i32:$src2, i32:$src2_modifiers)))),
279+
(V_ALIGNBYTE_B32_opsel_e64 i32:$src0_modifiers, VSrc_b32:$src0,
280+
i32:$src1_modifiers, VSrc_b32:$src1,
281+
i32:$src2_modifiers, VGPR_32:$src2)
282+
>;
283+
268284
let True16Predicate = UseFakeTrue16Insts in
269285
def : GCNPat <
270286
(i32 (int_amdgcn_alignbyte (i32 (VOP3OpSelMods i32:$src0, i32:$src0_modifiers)),
@@ -1954,6 +1970,9 @@ let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
19541970
}
19551971
} // End AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10"
19561972

1973+
defm V_ALIGNBIT_B32_opsel : VOP3OpSel_Real_gfx10_with_name<0x14e, "V_ALIGNBIT_B32_opsel", "v_alignbit_b32">;
1974+
defm V_ALIGNBYTE_B32_opsel : VOP3OpSel_Real_gfx10_with_name<0x14f, "V_ALIGNBYTE_B32_opsel", "v_alignbyte_b32">;
1975+
19571976
defm V_READLANE_B32 : VOP3_Real_No_Suffix_gfx10<0x360>;
19581977

19591978
let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in {
@@ -2104,8 +2123,8 @@ defm V_BFI_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14a>;
21042123
defm V_FMA_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x14b>;
21052124
defm V_FMA_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x14c>;
21062125
defm V_LERP_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x14d>;
2107-
defm V_ALIGNBIT_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14e>;
2108-
defm V_ALIGNBYTE_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14f>;
2126+
defm V_ALIGNBIT_B32 : VOP3_Real_gfx6_gfx7<0x14e>;
2127+
defm V_ALIGNBYTE_B32 : VOP3_Real_gfx6_gfx7<0x14f>;
21092128
defm V_MULLIT_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x150>;
21102129
defm V_MIN3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x151>;
21112130
defm V_MIN3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x152>;
@@ -2248,6 +2267,17 @@ multiclass VOP3_Real_BITOP3_gfx9<bits<10> op, string AsmName, bit isSingle = 0>
22482267
}
22492268
}
22502269

2270+
// Instructions such as v_alignbyte_b32 allows op_sel in gfx9, but not in vi.
2271+
// The following is created to support that.
2272+
multiclass VOP3OpSel_Real_gfx9_with_name<bits<10> op, string opName, string AsmName> {
2273+
defvar psName = opName#"_e64";
2274+
def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(psName), SIEncodingFamily.VI>, // note: encoding family is VI
2275+
VOP3OpSel_gfx9 <op, !cast<VOP3_Pseudo>(psName).Pfl> {
2276+
VOP3_Pseudo ps = !cast<VOP3_Pseudo>(psName);
2277+
let AsmString = AsmName # ps.AsmOperands;
2278+
}
2279+
}
2280+
22512281
} // End AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9"
22522282

22532283
defm V_MAD_U64_U32 : VOP3be_Real_vi <0x1E8>;
@@ -2267,8 +2297,10 @@ defm V_BFI_B32 : VOP3_Real_vi <0x1ca>;
22672297
defm V_FMA_F32 : VOP3_Real_vi <0x1cb>;
22682298
defm V_FMA_F64 : VOP3_Real_vi <0x1cc>;
22692299
defm V_LERP_U8 : VOP3_Real_vi <0x1cd>;
2300+
let SubtargetPredicate = isGFX8Only in {
22702301
defm V_ALIGNBIT_B32 : VOP3_Real_vi <0x1ce>;
22712302
defm V_ALIGNBYTE_B32 : VOP3_Real_vi <0x1cf>;
2303+
}
22722304
defm V_MIN3_F32 : VOP3_Real_vi <0x1d0>;
22732305
defm V_MIN3_I32 : VOP3_Real_vi <0x1d1>;
22742306
defm V_MIN3_U32 : VOP3_Real_vi <0x1d2>;
@@ -2313,6 +2345,9 @@ defm V_INTERP_P2_LEGACY_F16 : VOP3Interp_F16_Real_gfx9 <0x276, "V_INTERP_P2_F16"
23132345
defm V_MAD_LEGACY_U16 : VOP3_F16_Real_gfx9 <0x1eb, "V_MAD_U16", "v_mad_legacy_u16">;
23142346
defm V_MAD_LEGACY_I16 : VOP3_F16_Real_gfx9 <0x1ec, "V_MAD_I16", "v_mad_legacy_i16">;
23152347

2348+
defm V_ALIGNBIT_B32_opsel : VOP3OpSel_Real_gfx9_with_name <0x1ce, "V_ALIGNBIT_B32_opsel", "v_alignbit_b32">;
2349+
defm V_ALIGNBYTE_B32_opsel : VOP3OpSel_Real_gfx9_with_name <0x1cf, "V_ALIGNBYTE_B32_opsel", "v_alignbyte_b32">;
2350+
23162351
defm V_MAD_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x203, "v_mad_f16">;
23172352
defm V_MAD_U16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x204, "v_mad_u16">;
23182353
defm V_MAD_I16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x205, "v_mad_i16">;

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bswap.mir‎

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7 %s
33
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
4+
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
5+
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
46

57
---
68
name: bswap_i32_vv
@@ -19,13 +21,30 @@ body: |
1921
; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16711935
2022
; GFX7-NEXT: [[V_BFI_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFI_B32_e64 [[S_MOV_B32_]], [[V_ALIGNBIT_B32_e64_1]], [[V_ALIGNBIT_B32_e64_]], implicit $exec
2123
; GFX7-NEXT: S_ENDPGM 0, implicit [[V_BFI_B32_e64_]]
24+
;
2225
; GFX8-LABEL: name: bswap_i32_vv
2326
; GFX8: liveins: $vgpr0
2427
; GFX8-NEXT: {{ $}}
2528
; GFX8-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2629
; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 66051
2730
; GFX8-NEXT: [[V_PERM_B32_e64_:%[0-9]+]]:vgpr_32 = V_PERM_B32_e64 0, [[COPY]], [[S_MOV_B32_]], implicit $exec
2831
; GFX8-NEXT: S_ENDPGM 0, implicit [[V_PERM_B32_e64_]]
32+
;
33+
; GFX9-LABEL: name: bswap_i32_vv
34+
; GFX9: liveins: $vgpr0
35+
; GFX9-NEXT: {{ $}}
36+
; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
37+
; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 66051
38+
; GFX9-NEXT: [[V_PERM_B32_e64_:%[0-9]+]]:vgpr_32 = V_PERM_B32_e64 0, [[COPY]], [[S_MOV_B32_]], implicit $exec
39+
; GFX9-NEXT: S_ENDPGM 0, implicit [[V_PERM_B32_e64_]]
40+
;
41+
; GFX10-LABEL: name: bswap_i32_vv
42+
; GFX10: liveins: $vgpr0
43+
; GFX10-NEXT: {{ $}}
44+
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
45+
; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 66051
46+
; GFX10-NEXT: [[V_PERM_B32_e64_:%[0-9]+]]:vgpr_32 = V_PERM_B32_e64 0, [[COPY]], [[S_MOV_B32_]], implicit $exec
47+
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_PERM_B32_e64_]]
2948
%0:vgpr(s32) = COPY $vgpr0
3049
%1:vgpr(s32) = G_BSWAP %0
3150
S_ENDPGM 0, implicit %1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir‎

Lines changed: 20 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
33
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
4-
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
5-
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
4+
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
5+
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
66
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefixes=GFX11 %s
77

88
---
@@ -24,6 +24,24 @@ body: |
2424
; GCN-NEXT: [[V_ALIGNBIT_B32_e64_:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
2525
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ALIGNBIT_B32_e64_]]
2626
;
27+
; GFX9-LABEL: name: fshr_s32
28+
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
29+
; GFX9-NEXT: {{ $}}
30+
; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
31+
; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
32+
; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
33+
; GFX9-NEXT: [[V_ALIGNBIT_B32_opsel_e64_:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_opsel_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
34+
; GFX9-NEXT: S_ENDPGM 0, implicit [[V_ALIGNBIT_B32_opsel_e64_]]
35+
;
36+
; GFX10-LABEL: name: fshr_s32
37+
; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
38+
; GFX10-NEXT: {{ $}}
39+
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
40+
; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
41+
; GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
42+
; GFX10-NEXT: [[V_ALIGNBIT_B32_opsel_e64_:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_opsel_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
43+
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_ALIGNBIT_B32_opsel_e64_]]
44+
;
2745
; GFX11-LABEL: name: fshr_s32
2846
; GFX11: liveins: $vgpr0, $vgpr1, $vgpr2
2947
; GFX11-NEXT: {{ $}}

‎llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -766,10 +766,10 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
766766
; GFX90A-NEXT: renamable $vgpr10 = COPY renamable $sgpr22, implicit $exec
767767
; GFX90A-NEXT: renamable $vgpr12_vgpr13 = DS_READ_B64_gfx9 killed renamable $vgpr10, 0, 0, implicit $exec :: (load (s64) from %ir.8, addrspace 3)
768768
; GFX90A-NEXT: renamable $vgpr10 = COPY renamable $sgpr46, implicit $exec
769-
; GFX90A-NEXT: renamable $vgpr11 = V_ALIGNBIT_B32_e64 killed $sgpr47, killed $vgpr10, 1, implicit $exec
770-
; GFX90A-NEXT: renamable $vgpr52 = V_ALIGNBIT_B32_e64 $vgpr17, $vgpr16, 1, implicit $exec
769+
; GFX90A-NEXT: renamable $vgpr11 = V_ALIGNBIT_B32_opsel_e64 0, killed $sgpr47, 0, killed $vgpr10, 0, 1, 0, 0, implicit $exec
770+
; GFX90A-NEXT: renamable $vgpr52 = V_ALIGNBIT_B32_opsel_e64 0, $vgpr17, 0, $vgpr16, 0, 1, 0, 0, implicit $exec
771771
; GFX90A-NEXT: renamable $vgpr17 = V_CNDMASK_B32_e64 0, 0, 0, 1, $sgpr12_sgpr13, implicit $exec
772-
; GFX90A-NEXT: renamable $vgpr15 = V_ALIGNBIT_B32_e64 $vgpr15, $vgpr14, 1, implicit $exec
772+
; GFX90A-NEXT: renamable $vgpr15 = V_ALIGNBIT_B32_opsel_e64 0, $vgpr15, 0, $vgpr14, 0, 1, 0, 0, implicit $exec
773773
; GFX90A-NEXT: renamable $sgpr52_sgpr53 = S_XOR_B64 $exec, -1, implicit-def dead $scc
774774
; GFX90A-NEXT: renamable $sgpr62_sgpr63 = S_OR_B64 renamable $sgpr36_sgpr37, $exec, implicit-def dead $scc
775775
; GFX90A-NEXT: renamable $vgpr10 = COPY renamable $vgpr14, implicit $exec

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll‎

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
22
; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3+
; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
34
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-TRUE16 %s
45
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-FAKE16 %s
56

@@ -19,6 +20,18 @@ define amdgpu_kernel void @v_alignbyte_b32(ptr addrspace(1) %out, i32 %src1, i32
1920
; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
2021
; GCN-NEXT: s_endpgm
2122
;
23+
; GFX10-LABEL: v_alignbyte_b32:
24+
; GFX10: ; %bb.0:
25+
; GFX10-NEXT: s_clause 0x1
26+
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
27+
; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
28+
; GFX10-NEXT: v_mov_b32_e32 v1, 0
29+
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
30+
; GFX10-NEXT: v_mov_b32_e32 v0, s2
31+
; GFX10-NEXT: v_alignbyte_b32 v0, s0, s1, v0
32+
; GFX10-NEXT: global_store_dword v1, v0, s[4:5]
33+
; GFX10-NEXT: s_endpgm
34+
;
2235
; GFX11-TRUE16-LABEL: v_alignbyte_b32:
2336
; GFX11-TRUE16: ; %bb.0:
2437
; GFX11-TRUE16-NEXT: s_clause 0x1
@@ -73,6 +86,24 @@ define amdgpu_kernel void @v_alignbyte_b32_2(ptr addrspace(1) %out, ptr addrspac
7386
; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
7487
; GCN-NEXT: s_endpgm
7588
;
89+
; GFX10-LABEL: v_alignbyte_b32_2:
90+
; GFX10: ; %bb.0:
91+
; GFX10-NEXT: s_clause 0x1
92+
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
93+
; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
94+
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
95+
; GFX10-NEXT: v_mov_b32_e32 v2, 0
96+
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
97+
; GFX10-NEXT: global_load_dword v1, v0, s[2:3] glc dlc
98+
; GFX10-NEXT: s_waitcnt vmcnt(0)
99+
; GFX10-NEXT: global_load_dword v0, v0, s[6:7] glc dlc
100+
; GFX10-NEXT: s_waitcnt vmcnt(0)
101+
; GFX10-NEXT: s_load_dword s2, s[4:5], 0x3c
102+
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
103+
; GFX10-NEXT: v_alignbyte_b32 v0, v1, v0, s2
104+
; GFX10-NEXT: global_store_dword v2, v0, s[0:1]
105+
; GFX10-NEXT: s_endpgm
106+
;
76107
; GFX11-TRUE16-LABEL: v_alignbyte_b32_2:
77108
; GFX11-TRUE16: ; %bb.0:
78109
; GFX11-TRUE16-NEXT: s_clause 0x1

‎llvm/test/MC/AMDGPU/gfx10_asm_vop3.s‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3628,6 +3628,18 @@ v_alignbit_b32 v5, v1, v2, exec_lo
36283628
v_alignbit_b32 v5, v1, v2, exec_hi
36293629
// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0x05,0xfe,0x01]
36303630

3631+
v_alignbit_b32 v5, v1, v2, v3 op_sel:[1]
3632+
// GFX10: v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x4e,0xd5,0x01,0x05,0x0e,0x04]
3633+
3634+
v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1]
3635+
// GFX10: v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1,0,0] ; encoding: [0x05,0x18,0x4e,0xd5,0x01,0x05,0x0e,0x04]
3636+
3637+
v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1,1]
3638+
// GFX10: v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1,1,0] ; encoding: [0x05,0x38,0x4e,0xd5,0x01,0x05,0x0e,0x04]
3639+
3640+
v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1,1,1]
3641+
// GFX10: v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x4e,0xd5,0x01,0x05,0x0e,0x04]
3642+
36313643
v_alignbyte_b32 v5, v1, v2, v3
36323644
// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0x05,0x0e,0x04]
36333645

@@ -3715,6 +3727,18 @@ v_alignbyte_b32 v5, v1, v2, exec_lo
37153727
v_alignbyte_b32 v5, v1, v2, exec_hi
37163728
// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0x05,0xfe,0x01]
37173729

3730+
v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1]
3731+
// GFX10: v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x4f,0xd5,0x01,0x05,0x0e,0x04]
3732+
3733+
v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1]
3734+
// GFX10: v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,0,0] ; encoding: [0x05,0x18,0x4f,0xd5,0x01,0x05,0x0e,0x04]
3735+
3736+
v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,1]
3737+
// GFX10: v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,1,0] ; encoding: [0x05,0x38,0x4f,0xd5,0x01,0x05,0x0e,0x04]
3738+
3739+
v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,1,1]
3740+
// GFX10: v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x4f,0xd5,0x01,0x05,0x0e,0x04]
3741+
37183742
v_mullit_f32 v5, v1, v2, v3
37193743
// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0x0e,0x04]
37203744

‎llvm/test/MC/AMDGPU/gfx7_err_pos.s‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -44,3 +44,16 @@ s_load_dword s5, s[2:3], glc
4444
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: cache policy is not supported for SMRD instructions
4545
// CHECK-NEXT:{{^}}s_load_dword s5, s[2:3], glc
4646
// CHECK-NEXT:{{^}} ^
47+
48+
//==============================================================================
49+
// not a valid operand
50+
51+
v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1,1,1]
52+
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
53+
// CHECK-NEXT:{{^}}v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1,1,1]
54+
// CHECK-NEXT:{{^}} ^
55+
56+
v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,1,1]
57+
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
58+
// CHECK-NEXT:{{^}}v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,1,1]
59+
// CHECK-NEXT:{{^}} ^

‎llvm/test/MC/AMDGPU/gfx8_err_pos.s‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49,3 +49,13 @@ v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PRESERV
4949
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
5050
// CHECK-NEXT:{{^}}v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 src1_sel:WORD_0
5151
// CHECK-NEXT:{{^}} ^
52+
53+
v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1,1,1]
54+
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
55+
// CHECK-NEXT:{{^}}v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1,1,1]
56+
// CHECK-NEXT:{{^}} ^
57+
58+
v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,1,1]
59+
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
60+
// CHECK-NEXT:{{^}}v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,1,1]
61+
// CHECK-NEXT:{{^}} ^

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