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1 parent b8f24a5 commit a2419acCopy full SHA for a2419ac
llvm/lib/Target/Hexagon/HexagonGenWideningVecInstr.cpp
@@ -349,7 +349,7 @@ Intrinsic::ID HexagonGenWideningVecInstr::getIntrinsic(
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llvm_unreachable("Incorrect input and output operand sizes");
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case OP_Mul:
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- assert(ResEltSize = 2 * InEltSize);
+ assert(ResEltSize == 2 * InEltSize);
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// Enter inside 'if' block when one of the operand is constant vector
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if (IsConstScalar) {
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// When inputs are of 8bit type and output is 16bit type, enter 'if' block
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