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castiglikcloudy0717
castigli
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kcloudy0717
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[NVGPU] Fix nvdsl examples - take 2 (llvm#167321)
This PR re-lands llvm#156830 This PR aims at fixing the nvdsl examples which got a bit out of sync not being tested in the CI. The fixed bugs were related to the following PRs: - move to nanobind llvm#118583 - split gpu module initialization llvm#135478 - gpu dialect python API change llvm#163883
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‎mlir/test/Examples/NVGPU/Ch0.py‎

Lines changed: 23 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,9 @@
11
# RUN: env SUPPORT_LIB=%mlir_cuda_runtime \
2-
# RUN: %PYTHON %s | FileCheck %s
2+
# RUN: sh -c 'if [[ "%mlir_run_cuda_sm90_tests" == "1" ]]; \
3+
# RUN: then %PYTHON %s | FileCheck %s; \
4+
# RUN: else export MLIR_NVDSL_PRINT_IR=1; \
5+
# RUN: %PYTHON %s | FileCheck %s --check-prefix=DUMPIR; fi'
6+
37

48
# ===----------------------------------------------------------------------===//
59
# Chapter 0 : Hello World
@@ -33,7 +37,7 @@ def kernel():
3337
# + operator generates arith.addi
3438
myValue = alpha + tidx
3539
# Print from a GPU thread
36-
gpu.printf("GPU thread %llu has %llu\n", [tidx, myValue])
40+
gpu.printf("GPU thread %llu has %llu\n", tidx, myValue)
3741

3842
# 3. Call the GPU kernel
3943
kernel()
@@ -43,8 +47,24 @@ def kernel():
4347
# 4. The `mlir_func` decorator JIT compiles the IR and executes the MLIR function.
4448
main(alpha)
4549

46-
4750
# CHECK: GPU thread 0 has 100
4851
# CHECK: GPU thread 1 has 101
4952
# CHECK: GPU thread 2 has 102
5053
# CHECK: GPU thread 3 has 103
54+
55+
# DUMPIR: func.func @main(%arg0: index) attributes {llvm.emit_c_interface} {
56+
# DUMPIR: %[[C0_I32:.*]] = arith.constant 0 : i32
57+
# DUMPIR: %[[C1:.*]] = arith.constant 1 : index
58+
# DUMPIR: %[[C1_0:.*]] = arith.constant 1 : index
59+
# DUMPIR: %[[C1_1:.*]] = arith.constant 1 : index
60+
# DUMPIR: %[[C4:.*]] = arith.constant 4 : index
61+
# DUMPIR: %[[C1_2:.*]] = arith.constant 1 : index
62+
# DUMPIR: %[[C1_3:.*]] = arith.constant 1 : index
63+
# DUMPIR: gpu.launch blocks(%arg1, %arg2, %arg3) in (%arg7 = %[[C1]], %arg8 = %[[C1_0]], %arg9 = %[[C1_1]]) threads(%arg4, %arg5, %arg6) in (%arg10 = %[[C4]], %arg11 = %[[C1_2]], %arg12 = %[[C1_3]]) dynamic_shared_memory_size %[[C0_I32]] {
64+
# DUMPIR: %[[TIDX:.*]] = gpu.thread_id x
65+
# DUMPIR: %[[MYVAL:.*]] = arith.addi %arg0, %[[TIDX]] : index
66+
# DUMPIR: gpu.printf "GPU thread %llu has %llu\0A", %[[TIDX]], %[[MYVAL]] : index, index
67+
# DUMPIR: gpu.terminator
68+
# DUMPIR: }
69+
# DUMPIR: return
70+
# DUMPIR: }

‎mlir/test/Examples/NVGPU/Ch1.py‎

Lines changed: 34 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,9 @@
11
# RUN: env SUPPORT_LIB=%mlir_cuda_runtime \
2-
# RUN: %PYTHON %s | FileCheck %s
2+
# RUN: sh -c 'if [[ "%mlir_run_cuda_sm90_tests" == "1" ]]; \
3+
# RUN: then %PYTHON %s | FileCheck %s; \
4+
# RUN: else export MLIR_NVDSL_PRINT_IR=1; \
5+
# RUN: %PYTHON %s | FileCheck %s --check-prefix=DUMPIR; fi'
6+
37

48
# ===----------------------------------------------------------------------===//
59
# Chapter 1 : 2D Saxpy
@@ -24,12 +28,12 @@
2428
def saxpy(x, y, alpha):
2529
# 1. Use MLIR GPU dialect to allocate and copy memory
2630
token_ty = gpu.AsyncTokenType.get()
27-
t1 = gpu.wait(token_ty, [])
31+
t1 = gpu.wait([])
2832
x_dev, t2 = gpu.alloc(x.type, token_ty, [t1], [], [])
2933
y_dev, t3 = gpu.alloc(y.type, token_ty, [t2], [], [])
3034
t4 = gpu.memcpy(token_ty, [t3], x_dev, x)
3135
t5 = gpu.memcpy(token_ty, [t4], y_dev, y)
32-
t6 = gpu.wait(token_ty, [t5])
36+
t6 = gpu.wait([t5])
3337

3438
# 2. Compute 2D SAXPY kernel
3539
@NVDSL.mlir_gpu_launch(grid=(M, 1, 1), block=(N, 1, 1))
@@ -47,7 +51,7 @@ def saxpy_kernel():
4751
saxpy_kernel()
4852

4953
t7 = gpu.memcpy(token_ty, [t6], y, y_dev)
50-
gpu.wait(token_ty, [t7])
54+
gpu.wait([t7])
5155

5256

5357
# 3. Pass numpy arrays to MLIR
@@ -56,11 +60,32 @@ def saxpy_kernel():
5660
alpha = 2.0
5761
x = np.random.randn(M, N).astype(np.float32)
5862
y = np.ones((M, N), np.float32)
63+
5964
saxpy(x, y, alpha)
6065

61-
# 4. Verify MLIR with reference computation
62-
ref = np.ones((M, N), np.float32)
63-
ref += x * alpha
64-
np.testing.assert_allclose(y, ref, rtol=5e-03, atol=1e-01)
65-
print("PASS")
66+
if os.getenv("MLIR_NVDSL_PRINT_IR") != "1":
67+
# 4. Verify MLIR with reference computation
68+
ref = np.ones((M, N), np.float32)
69+
ref += x * alpha
70+
np.testing.assert_allclose(y, ref, rtol=5e-03, atol=1e-01)
71+
print("PASS")
6672
# CHECK-NOT: Mismatched elements
73+
# CHECK: PASS
74+
75+
# DUMPIR: func.func @saxpy(%[[ARG0:.*]]: memref<256x32xf32>, %[[ARG1:.*]]: memref<256x32xf32>, %[[ARG2:.*]]: f32) attributes {llvm.emit_c_interface} {
76+
# DUMPIR: %[[WAIT0:.*]] = gpu.wait async
77+
# DUMPIR: %[[MEMREF:.*]], %[[ASYNC0:.*]] = gpu.alloc async [%[[WAIT0]]] () : memref<256x32xf32>
78+
# DUMPIR: %[[MEMREF0:.*]], %[[ASYNC1:.*]] = gpu.alloc async [%[[ASYNC0]]] () : memref<256x32xf32>
79+
# DUMPIR: %[[MEMCPY1:.*]] = gpu.memcpy async [%[[ASYNC1]]] %[[MEMREF]], %[[ARG0]] : memref<256x32xf32>, memref<256x32xf32>
80+
# DUMPIR: %[[MEMCPY2:.*]] = gpu.memcpy async [%[[MEMCPY1]]] %[[MEMREF0]], %[[ARG1]] : memref<256x32xf32>, memref<256x32xf32>
81+
# DUMPIR: %[[WAIT1:.*]] = gpu.wait async [%[[MEMCPY2]]]
82+
# DUMPIR: %[[LD0:.*]] = memref.load %[[MEMREF]][%{{.*}}, %{{.*}}] : memref<256x32xf32>
83+
# DUMPIR: %[[LD1:.*]] = memref.load %[[MEMREF0]][%{{.*}}, %{{.*}}] : memref<256x32xf32>
84+
# DUMPIR: %[[MUL:.*]] = arith.mulf %[[LD0]], %[[ARG2]] : f32
85+
# DUMPIR: %[[ADD:.*]] = arith.addf %[[LD1]], %[[MUL]] : f32
86+
# DUMPIR: memref.store %[[ADD]], %[[MEMREF0]][%{{.*}}, %{{.*}}] : memref<256x32xf32>
87+
# DUMPIR: gpu.terminator
88+
# DUMPIR: %[[MEMCPY3:.*]] = gpu.memcpy async [%[[WAIT1]]] %[[ARG1]], %[[MEMREF0]] : memref<256x32xf32>, memref<256x32xf32>
89+
# DUMPIR: %[[WAIT2:.*]] = gpu.wait async [%[[MEMCPY3]]]
90+
# DUMPIR: return
91+
# DUMPIR: }

‎mlir/test/Examples/NVGPU/Ch2.py‎

Lines changed: 50 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,9 @@
11
# RUN: env SUPPORT_LIB=%mlir_cuda_runtime \
2-
# RUN: %PYTHON %s | FileCheck %s
2+
# RUN: sh -c 'if [[ "%mlir_run_cuda_sm90_tests" == "1" ]]; \
3+
# RUN: then %PYTHON %s | FileCheck %s; \
4+
# RUN: else export MLIR_NVDSL_PRINT_IR=1; \
5+
# RUN: %PYTHON %s | FileCheck %s --check-prefix=DUMPIR; fi'
6+
37

48
# ===----------------------------------------------------------------------===//
59
# Chapter 2 : 2D Saxpy with TMA
@@ -28,12 +32,12 @@
2832
@NVDSL.mlir_func
2933
def saxpy(x, y, alpha):
3034
token_ty = gpu.AsyncTokenType.get()
31-
t1 = gpu.wait(token_ty, [])
35+
t1 = gpu.wait([])
3236
x_dev, t2 = gpu.alloc(x.type, token_ty, [t1], [], [])
3337
y_dev, t3 = gpu.alloc(y.type, token_ty, [t2], [], [])
3438
t4 = gpu.memcpy(token_ty, [t3], x_dev, x)
3539
t5 = gpu.memcpy(token_ty, [t4], y_dev, y)
36-
t6 = gpu.wait(token_ty, [t5])
40+
t6 = gpu.wait([t5])
3741

3842
x_tma = TMA([1, N], x.type)
3943
y_tma = TMA([1, N], y.type)
@@ -74,7 +78,7 @@ def saxpy_tma_kernel():
7478
saxpy_tma_kernel()
7579

7680
t7 = gpu.memcpy(token_ty, [t6], y, y_dev)
77-
gpu.wait(token_ty, [t7])
81+
gpu.wait([t7])
7882

7983

8084
# 3. Pass numpy arrays to MLIR
@@ -85,9 +89,46 @@ def saxpy_tma_kernel():
8589
y = np.ones((M, N), np.float32)
8690
saxpy(x, y, alpha)
8791

88-
# 4. Verify MLIR with reference computation
89-
ref = np.ones((M, N), np.float32)
90-
ref += x * alpha
91-
np.testing.assert_allclose(y, ref, rtol=5e-03, atol=1e-01)
92-
print("PASS")
92+
if os.getenv("MLIR_NVDSL_PRINT_IR") != "1":
93+
# 4. Verify MLIR with reference computation
94+
ref = np.ones((M, N), np.float32)
95+
ref += x * alpha
96+
np.testing.assert_allclose(y, ref, rtol=5e-03, atol=1e-01)
97+
print("PASS")
9398
# CHECK-NOT: Mismatched elements
99+
# CHECK: PASS
100+
101+
# DUMPIR: func.func @saxpy(%{{.*}}: memref<256x32xf32>, %[[ARG1:.*]]: memref<256x32xf32>, %[[ARG2:.*]]: f32) attributes {llvm.emit_c_interface} {
102+
# DUMPIR: %[[WAIT0:.*]] = gpu.wait async
103+
# DUMPIR: %[[MEMREF:.*]], %[[ASYNC0:.*]] = gpu.alloc async [%[[WAIT0]]] () : memref<256x32xf32>
104+
# DUMPIR: %[[CAST:.*]] = memref.cast %[[MEMREF]] : memref<256x32xf32> to memref<*xf32>
105+
# DUMPIR: %[[C1:.*]] = arith.constant 1 : index
106+
# DUMPIR: %[[C32:.*]] = arith.constant 32 : index
107+
# DUMPIR: %[[TMA0:.*]] = nvgpu.tma.create.descriptor %[[CAST]] box[%[[C1]], %[[C32]]] : memref<*xf32> -> <tensor = memref<1x32xf32, 3>, swizzle = none, l2promo = none, oob = zero, interleave = none>
108+
# DUMPIR: %[[C0:.*]] = arith.constant 0 : index
109+
# DUMPIR: %[[EQ:.*]] = arith.cmpi eq, %{{.*}}, %[[C0]] : index
110+
# DUMPIR: %[[MB:.*]] = nvgpu.mbarrier.create -> <memorySpace = #gpu.address_space<workgroup>>
111+
# DUMPIR: %[[C0_10:.*]] = arith.constant 0 : index
112+
# DUMPIR: %[[C1_11:.*]] = arith.constant 1 : index
113+
# DUMPIR: nvgpu.mbarrier.init %[[MB]][%[[C0_10]]], %[[C1_11]], predicate = %[[EQ]] : <memorySpace = #gpu.address_space<workgroup>>
114+
# DUMPIR: %[[DSM0:.*]] = gpu.dynamic_shared_memory : memref<?xi8, #gpu.address_space<workgroup>>
115+
# DUMPIR: %[[C0_12:.*]] = arith.constant 0 : index
116+
# DUMPIR: %[[VIEW:.*]] = memref.view %[[DSM0]][%[[C0_12]]][] : memref<?xi8, #gpu.address_space<workgroup>> to memref<1x32xf32, #gpu.address_space<workgroup>>
117+
# DUMPIR: %[[DSM1:.*]] = gpu.dynamic_shared_memory : memref<?xi8, #gpu.address_space<workgroup>>
118+
# DUMPIR: %[[C128:.*]] = arith.constant 128 : index
119+
# DUMPIR: %[[VIEW_13:.*]] = memref.view %[[DSM1]][%[[C128]]][] : memref<?xi8, #gpu.address_space<workgroup>> to memref<1x32xf32, #gpu.address_space<workgroup>>
120+
# DUMPIR: nvgpu.tma.async.load %[[TMA0]][%{{.*}}, %{{.*}}], %[[MB]][%{{.*}}] to %[[VIEW]], predicate = %[[EQ]] : <tensor = memref<1x32xf32, 3>, swizzle = none, l2promo = none, oob = zero, interleave = none>, <memorySpace = #gpu.address_space<workgroup>> -> memref<1x32xf32, #gpu.address_space<workgroup>>
121+
# DUMPIR: nvgpu.mbarrier.arrive.expect_tx %[[MB]][%{{.*}}], %{{.*}}, predicate = %[[EQ]] : <memorySpace = #gpu.address_space<workgroup>>
122+
# DUMPIR: %[[C0_20:.*]] = arith.constant 0 : index
123+
# DUMPIR: %[[C10000000:.*]] = arith.constant 10000000 : index
124+
# DUMPIR: %[[FALSE:.*]] = arith.constant false
125+
# DUMPIR: nvgpu.mbarrier.try_wait.parity %[[MB]][%[[C0_20]]], %[[FALSE]], %[[C10000000]] : <memorySpace = #gpu.address_space<workgroup>>
126+
# DUMPIR: %[[C0_21:.*]] = arith.constant 0 : index
127+
# DUMPIR: %[[LD0:.*]] = memref.load %[[VIEW]][%[[C0_21]], %{{.*}}] : memref<1x32xf32, #gpu.address_space<workgroup>>
128+
# DUMPIR: %[[C0_22:.*]] = arith.constant 0 : index
129+
# DUMPIR: %[[LD1:.*]] = memref.load %[[VIEW_13]][%[[C0_22]], %{{.*}}] : memref<1x32xf32, #gpu.address_space<workgroup>>
130+
# DUMPIR: memref.store %{{.*}}, %{{.*}}[%{{.*}}, %{{.*}}] : memref<256x32xf32>
131+
# DUMPIR: %[[MEMCPY3:.*]] = gpu.memcpy async [%{{.*}}] %[[ARG1]], %{{.*}} : memref<256x32xf32>, memref<256x32xf32>
132+
# DUMPIR: %{{.*}} = gpu.wait async [%[[MEMCPY3]]]
133+
# DUMPIR: return
134+
# DUMPIR: }

‎mlir/test/Examples/NVGPU/Ch3.py‎

Lines changed: 77 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,9 @@
11
# RUN: env SUPPORT_LIB=%mlir_cuda_runtime \
2-
# RUN: %PYTHON %s | FileCheck %s
2+
# RUN: sh -c 'if [[ "%mlir_run_cuda_sm90_tests" == "1" ]]; \
3+
# RUN: then %PYTHON %s | FileCheck %s; \
4+
# RUN: else export MLIR_NVDSL_PRINT_IR=1; \
5+
# RUN: %PYTHON %s | FileCheck %s --check-prefix=DUMPIR; fi'
6+
37

48
# ===----------------------------------------------------------------------===//
59
# Chapter 3 : GEMM 128x128x64 with Tensor Core
@@ -60,13 +64,13 @@ def tma_load(
6064
@NVDSL.mlir_func
6165
def gemm_128_128_64(a, b, d):
6266
token_ty = gpu.AsyncTokenType.get()
63-
t1 = gpu.wait(token_ty, [])
67+
t1 = gpu.wait([])
6468
a_dev, t2 = gpu.alloc(a.type, token_ty, [t1], [], [])
6569
b_dev, t3 = gpu.alloc(b.type, token_ty, [t2], [], [])
6670
d_dev, t4 = gpu.alloc(d.type, token_ty, [t3], [], [])
6771
t5 = gpu.memcpy(token_ty, [t4], a_dev, a)
6872
t6 = gpu.memcpy(token_ty, [t5], b_dev, b)
69-
t7 = gpu.wait(token_ty, [t6])
73+
t7 = gpu.wait([t6])
7074

7175
sw = nvgpu.TensorMapSwizzleKind.SWIZZLE_128B
7276
a_tma = TMA([128, 64], a.type, swizzle=sw)
@@ -111,7 +115,7 @@ def gemm_tma_kernel():
111115
gemm_tma_kernel()
112116

113117
t8 = gpu.memcpy(token_ty, [t7], d, d_dev)
114-
gpu.wait(None, [t8])
118+
gpu.wait([t8])
115119

116120

117121
# Python pass arguments to MLIR
@@ -123,7 +127,73 @@ def gemm_tma_kernel():
123127
d = np.zeros((M, N), np.float32)
124128
gemm_128_128_64(a, b, d)
125129

126-
ref_d = a.astype(np.float16) @ b.astype(np.float16)
127-
np.testing.assert_allclose(d, ref_d, rtol=5e-03, atol=1e-01)
128-
print("PASS")
130+
if os.getenv("MLIR_NVDSL_PRINT_IR") != "1":
131+
# Verify MLIR program with reference computation in python
132+
ref_d = a.astype(np.float16) @ b.astype(np.float16)
133+
np.testing.assert_allclose(d, ref_d, rtol=5e-03, atol=1e-01)
134+
print("PASS")
129135
# CHECK-NOT: Mismatched elements
136+
# CHECK: PASS
137+
138+
# DUMPIR: func.func @gemm_128_128_64(%{{.*}}: memref<128x64xf16>, %{{.*}}: memref<64x128xf16>, %[[ARG2:.*]]: memref<128x128xf32>) attributes {llvm.emit_c_interface} {
139+
# DUMPIR: %[[C128:.*]] = arith.constant 128 : index
140+
# DUMPIR: %[[C64:.*]] = arith.constant 64 : index
141+
# DUMPIR: %[[TMA0:.*]] = nvgpu.tma.create.descriptor %{{.*}} box[%[[C128]], %[[C64]]] : memref<*xf16> -> <tensor = memref<128x64xf16, 3>, swizzle = swizzle_128b, l2promo = none, oob = zero, interleave = none>
142+
# DUMPIR: %[[CAST1:.*]] = memref.cast %{{.*}} : memref<64x128xf16> to memref<*xf16>
143+
# DUMPIR: %[[C64_5:.*]] = arith.constant 64 : index
144+
# DUMPIR: %[[C64_6:.*]] = arith.constant 64 : index
145+
# DUMPIR: %[[TMA1:.*]] = nvgpu.tma.create.descriptor %[[CAST1]] box[%[[C64_5]], %[[C64_6]]] : memref<*xf16> -> <tensor = memref<64x64xf16, 3>, swizzle = swizzle_128b, l2promo = none, oob = zero, interleave = none>
146+
# DUMPIR: %[[THREADID:.*]] = gpu.thread_id x
147+
# DUMPIR: %[[MB:.*]] = nvgpu.mbarrier.create -> <memorySpace = #gpu.address_space<workgroup>>
148+
# DUMPIR: %[[C0:.*]] = arith.constant 0 : index
149+
# DUMPIR: %[[EQ:.*]] = arith.cmpi eq, %[[THREADID]], %[[C0]] : index
150+
# DUMPIR: %[[C0_12:.*]] = arith.constant 0 : index
151+
# DUMPIR: %[[C1_13:.*]] = arith.constant 1 : index
152+
# DUMPIR: nvgpu.mbarrier.init %[[MB]][%[[C0_12]]], %[[C1_13]], predicate = %[[EQ]] : <memorySpace = #gpu.address_space<workgroup>>
153+
# DUMPIR: nvgpu.tma.prefetch.descriptor %[[TMA0]], predicate = %[[EQ]] : <tensor = memref<128x64xf16, 3>, swizzle = swizzle_128b, l2promo = none, oob = zero, interleave = none>
154+
# DUMPIR: nvgpu.tma.prefetch.descriptor %[[TMA1]], predicate = %[[EQ]] : <tensor = memref<64x64xf16, 3>, swizzle = swizzle_128b, l2promo = none, oob = zero, interleave = none>
155+
# DUMPIR: %[[DSM0:.*]] = gpu.dynamic_shared_memory : memref<?xi8, #gpu.address_space<workgroup>>
156+
# DUMPIR: %[[C0_14:.*]] = arith.constant 0 : index
157+
# DUMPIR: %[[VIEW:.*]] = memref.view %[[DSM0]][%[[C0_14]]][] : memref<?xi8, #gpu.address_space<workgroup>> to memref<128x64xf16, #gpu.address_space<workgroup>>
158+
# DUMPIR: %[[DSM1:.*]] = gpu.dynamic_shared_memory : memref<?xi8, #gpu.address_space<workgroup>>
159+
# DUMPIR: %[[C16384:.*]] = arith.constant 16384 : index
160+
# DUMPIR: %[[VIEW_15:.*]] = memref.view %[[DSM1]][%[[C16384]]][] : memref<?xi8, #gpu.address_space<workgroup>> to memref<64x128xf16, #gpu.address_space<workgroup>>
161+
# DUMPIR: %[[DSM2:.*]] = gpu.dynamic_shared_memory : memref<?xi8, #gpu.address_space<workgroup>>
162+
# DUMPIR: %[[C0_16:.*]] = arith.constant 0 : index
163+
# DUMPIR: %[[VIEW_17:.*]] = memref.view %[[DSM2]][%[[C0_16]]][] : memref<?xi8, #gpu.address_space<workgroup>> to memref<128x64xf16, #gpu.address_space<workgroup>>
164+
# DUMPIR: %[[DSM3:.*]] = gpu.dynamic_shared_memory : memref<?xi8, #gpu.address_space<workgroup>>
165+
# DUMPIR: %[[C16384_18:.*]] = arith.constant 16384 : index
166+
# DUMPIR: %[[VIEW_19:.*]] = memref.view %[[DSM3]][%[[C16384_18]]][] : memref<?xi8, #gpu.address_space<workgroup>> to memref<64x64xf16, #gpu.address_space<workgroup>>
167+
# DUMPIR: %[[DSM4:.*]] = gpu.dynamic_shared_memory : memref<?xi8, #gpu.address_space<workgroup>>
168+
# DUMPIR: %[[C24576:.*]] = arith.constant 24576 : index
169+
# DUMPIR: %[[VIEW_20:.*]] = memref.view %[[DSM4]][%[[C24576]]][] : memref<?xi8, #gpu.address_space<workgroup>> to memref<64x64xf16, #gpu.address_space<workgroup>>
170+
# DUMPIR: %[[C0_21:.*]] = arith.constant 0 : index
171+
# DUMPIR: %[[C32768:.*]] = arith.constant 32768 : index
172+
# DUMPIR: nvgpu.mbarrier.arrive.expect_tx %[[MB]][%[[C0_21]]], %[[C32768]], predicate = %[[EQ]] : <memorySpace = #gpu.address_space<workgroup>>
173+
# DUMPIR: %[[C0_22:.*]] = arith.constant 0 : index
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# DUMPIR: %[[C0_23:.*]] = arith.constant 0 : index
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# DUMPIR: %[[C0_24:.*]] = arith.constant 0 : index
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# DUMPIR: nvgpu.tma.async.load %[[TMA0]][%[[C0_23]], %[[C0_24]]], %[[MB]][%[[C0_22]]] to %[[VIEW_17]], predicate = %[[EQ]] : <tensor = memref<128x64xf16, 3>, swizzle = swizzle_128b, l2promo = none, oob = zero, interleave = none>, <memorySpace = #gpu.address_space<workgroup>> -> memref<128x64xf16, #gpu.address_space<workgroup>>
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# DUMPIR: %[[C0_25:.*]] = arith.constant 0 : index
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# DUMPIR: %[[C0_26:.*]] = arith.constant 0 : index
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# DUMPIR: %[[C0_27:.*]] = arith.constant 0 : index
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# DUMPIR: nvgpu.tma.async.load %[[TMA1]][%[[C0_26]], %[[C0_27]]], %[[MB]][%[[C0_25]]] to %[[VIEW_19]], predicate = %[[EQ]] : <tensor = memref<64x64xf16, 3>, swizzle = swizzle_128b, l2promo = none, oob = zero, interleave = none>, <memorySpace = #gpu.address_space<workgroup>> -> memref<64x64xf16, #gpu.address_space<workgroup>>
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# DUMPIR: %[[C0_28:.*]] = arith.constant 0 : index
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# DUMPIR: %[[C64_29:.*]] = arith.constant 64 : index
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# DUMPIR: %[[C0_30:.*]] = arith.constant 0 : index
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# DUMPIR: nvgpu.tma.async.load %[[TMA1]][%[[C64_29]], %[[C0_30]]], %[[MB]][%[[C0_28]]] to %[[VIEW_20]], predicate = %[[EQ]] : <tensor = memref<64x64xf16, 3>, swizzle = swizzle_128b, l2promo = none, oob = zero, interleave = none>, <memorySpace = #gpu.address_space<workgroup>> -> memref<64x64xf16, #gpu.address_space<workgroup>>
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# DUMPIR: %[[C0_31:.*]] = arith.constant 0 : index
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# DUMPIR: %[[C10000000:.*]] = arith.constant 10000000 : index
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# DUMPIR: %[[FALSE:.*]] = arith.constant false
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# DUMPIR: nvgpu.mbarrier.try_wait.parity %[[MB]][%[[C0_31]]], %[[FALSE]], %[[C10000000]] : <memorySpace = #gpu.address_space<workgroup>>
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# DUMPIR: %[[WG_ACC:.*]] = nvgpu.warpgroup.mma.init.accumulator -> <fragmented = vector<128x128xf32>>
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# DUMPIR: %[[GEN0:.*]] = nvgpu.warpgroup.generate.descriptor %[[VIEW]], %[[TMA0]] : memref<128x64xf16, #gpu.address_space<workgroup>>, <tensor = memref<128x64xf16, 3>, swizzle = swizzle_128b, l2promo = none, oob = zero, interleave = none> -> <tensor = memref<128x64xf16, #gpu.address_space<workgroup>>>
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# DUMPIR: %[[GEN1:.*]] = nvgpu.warpgroup.generate.descriptor %[[VIEW_15]], %[[TMA1]] : memref<64x128xf16, #gpu.address_space<workgroup>>, <tensor = memref<64x64xf16, 3>, swizzle = swizzle_128b, l2promo = none, oob = zero, interleave = none> -> <tensor = memref<64x128xf16, #gpu.address_space<workgroup>>>
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# DUMPIR: %[[MMA:.*]] = nvgpu.warpgroup.mma %[[GEN0]], %[[GEN1]], %[[WG_ACC]] {transposeB} : <tensor = memref<128x64xf16, #gpu.address_space<workgroup>>>, <tensor = memref<64x128xf16, #gpu.address_space<workgroup>>>, <fragmented = vector<128x128xf32>> -> <fragmented = vector<128x128xf32>>
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# DUMPIR: nvgpu.warpgroup.mma.store %[[MMA]], %{{.*}} : <fragmented = vector<128x128xf32>> to memref<128x128xf32>
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# DUMPIR: gpu.terminator
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# DUMPIR: }
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# DUMPIR: %[[CPY3:.*]] = gpu.memcpy async [%{{.*}}] %[[ARG2]], %{{.*}} : memref<128x128xf32>, memref<128x128xf32>
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# DUMPIR: gpu.wait async [%[[CPY3]]]
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# DUMPIR: return
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# DUMPIR: }

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