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AngeloGioacchino Del Regno
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arm64: dts: mediatek: mt8188: Address binding warnings for MDP3 nodes
Address various dt-binding warnings for most of the MDP3 nodes by adding and removing interrupts and power domains where required. Also, remove the mediatek,mt8195-mdp3-rdma fallback compatible from the main MDP3 RDMA node as the two have never really been fully compatible. Acked-by: Rob Herring (Arm) <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
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‎arch/arm64/boot/dts/mediatek/mt8188.dtsi

Lines changed: 31 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -2243,27 +2243,17 @@
22432243
};
22442244

22452245
dma-controller@14001000 {
2246-
compatible = "mediatek,mt8188-mdp3-rdma", "mediatek,mt8195-mdp3-rdma";
2246+
compatible = "mediatek,mt8188-mdp3-rdma";
22472247
reg = <0 0x14001000 0 0x1000>;
22482248
#dma-cells = <1>;
2249-
clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>,
2250-
<&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP0>,
2251-
<&topckgen CLK_TOP_CFGREG_F26M_VPP0>,
2252-
<&vppsys0 CLK_VPP0_WARP0_ASYNC_TX>,
2253-
<&vppsys0 CLK_VPP0_WARP0_RELAY>,
2254-
<&vppsys0 CLK_VPP0_WARP0_ASYNC>,
2255-
<&vppsys0 CLK_VPP02VPP1_RELAY>,
2256-
<&vppsys1 CLK_VPP1_VPP0_DL_ASYNC>,
2257-
<&vppsys1 CLK_VPP1_VPP0_DL1_RELAY>,
2258-
<&vppsys0 CLK_VPP0_VPP12VPP0_ASYNC>;
2249+
clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>;
22592250
mboxes = <&gce0 13 CMDQ_THR_PRIO_1>,
22602251
<&gce0 14 CMDQ_THR_PRIO_1>,
22612252
<&gce0 16 CMDQ_THR_PRIO_1>,
2262-
<&gce0 21 CMDQ_THR_PRIO_1>;
2263-
iommus = <&vpp_iommu M4U_PORT_L4_MDP_RDMA>,
2264-
<&vpp_iommu M4U_PORT_L4_MDP_WROT>;
2265-
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>,
2266-
<&spm MT8188_POWER_DOMAIN_VPPSYS1>;
2253+
<&gce0 21 CMDQ_THR_PRIO_1>,
2254+
<&gce0 22 CMDQ_THR_PRIO_1>;
2255+
iommus = <&vpp_iommu M4U_PORT_L4_MDP_RDMA>;
2256+
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
22672257
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
22682258
mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
22692259
<CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>;
@@ -2274,21 +2264,20 @@
22742264
compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg";
22752265
reg = <0 0x14002000 0 0x1000>;
22762266
clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
2277-
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
22782267
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
22792268
};
22802269

22812270
display@14004000 {
22822271
compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr";
22832272
reg = <0 0x14004000 0 0x1000>;
22842273
clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
2285-
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
22862274
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
22872275
};
22882276

22892277
display@14005000 {
22902278
compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal";
22912279
reg = <0 0x14005000 0 0x1000>;
2280+
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>;
22922281
clocks = <&vppsys0 CLK_VPP0_MDP_AAL>;
22932282
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
22942283
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
@@ -2298,21 +2287,22 @@
22982287
compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
22992288
reg = <0 0x14006000 0 0x1000>;
23002289
clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>;
2301-
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
23022290
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>;
2291+
mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>,
2292+
<CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE>;
23032293
};
23042294

23052295
display@14007000 {
23062296
compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp";
23072297
reg = <0 0x14007000 0 0x1000>;
23082298
clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
2309-
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
23102299
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
23112300
};
23122301

23132302
display@14008000 {
23142303
compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color";
23152304
reg = <0 0x14008000 0 0x1000>;
2305+
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
23162306
clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>;
23172307
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
23182308
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>;
@@ -2321,9 +2311,11 @@
23212311
display@14009000 {
23222312
compatible = "mediatek,mt8188-mdp3-ovl", "mediatek,mt8195-mdp3-ovl";
23232313
reg = <0 0x14009000 0 0x1000>;
2314+
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
23242315
clocks = <&vppsys0 CLK_VPP0_MDP_OVL>;
23252316
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
23262317
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>;
2318+
iommus = <&vpp_iommu M4U_PORT_L4_MDP_OVL>;
23272319
};
23282320

23292321
display@1400a000 {
@@ -2338,13 +2330,13 @@
23382330
compatible = "mediatek,mt8188-mdp3-tcc", "mediatek,mt8195-mdp3-tcc";
23392331
reg = <0 0x1400b000 0 0x1000>;
23402332
clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
2341-
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
23422333
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
23432334
};
23442335

23452336
display@1400c000 {
23462337
compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
23472338
reg = <0 0x1400c000 0 0x1000>;
2339+
#dma-cells = <1>;
23482340
clocks = <&vppsys0 CLK_VPP0_MDP_WROT>;
23492341
iommus = <&vpp_iommu M4U_PORT_L4_MDP_WROT>;
23502342
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
@@ -2394,29 +2386,23 @@
23942386
};
23952387

23962388
dma-controller@14f09000 {
2397-
compatible = "mediatek,mt8188-mdp3-rdma", "mediatek,mt8195-mdp3-rdma";
2389+
compatible = "mediatek,mt8188-mdp3-rdma";
23982390
reg = <0 0x14f09000 0 0x1000>;
23992391
#dma-cells = <1>;
2400-
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>,
2401-
<&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP1>,
2402-
<&topckgen CLK_TOP_CFGREG_F26M_VPP1>;
2403-
iommus = <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_RDMA>,
2404-
<&vdo_iommu M4U_PORT_L5_SVPP2_MDP_WROT>;
2392+
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>;
2393+
iommus = <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_RDMA>;
24052394
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
24062395
mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>;
24072396
mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>,
24082397
<CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE>;
24092398
};
24102399

24112400
dma-controller@14f0a000 {
2412-
compatible = "mediatek,mt8188-mdp3-rdma", "mediatek,mt8195-mdp3-rdma";
2401+
compatible = "mediatek,mt8188-mdp3-rdma";
24132402
reg = <0 0x14f0a000 0 0x1000>;
24142403
#dma-cells = <1>;
2415-
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>,
2416-
<&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP1>,
2417-
<&topckgen CLK_TOP_CFGREG_F26M_VPP1>;
2418-
iommus = <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_RDMA>,
2419-
<&vpp_iommu M4U_PORT_L6_SVPP3_MDP_WROT>;
2404+
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>;
2405+
iommus = <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_RDMA>;
24202406
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
24212407
mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>;
24222408
mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>,
@@ -2427,37 +2413,34 @@
24272413
compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg";
24282414
reg = <0 0x14f0c000 0 0x1000>;
24292415
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>;
2430-
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
24312416
mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>;
24322417
};
24332418

24342419
display@14f0d000 {
24352420
compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg";
24362421
reg = <0 0x14f0d000 0 0x1000>;
24372422
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>;
2438-
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
24392423
mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>;
24402424
};
24412425

24422426
display@14f0f000 {
24432427
compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr";
24442428
reg = <0 0x14f0f000 0 0x1000>;
24452429
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>;
2446-
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
24472430
mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>;
24482431
};
24492432

24502433
display@14f10000 {
24512434
compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr";
24522435
reg = <0 0x14f10000 0 0x1000>;
24532436
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>;
2454-
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
24552437
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>;
24562438
};
24572439

24582440
display@14f12000 {
24592441
compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal";
24602442
reg = <0 0x14f12000 0 0x1000>;
2443+
interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>;
24612444
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>;
24622445
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
24632446
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>;
@@ -2466,6 +2449,7 @@
24662449
display@14f13000 {
24672450
compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal";
24682451
reg = <0 0x14f13000 0 0x1000>;
2452+
interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>;
24692453
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>;
24702454
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
24712455
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>;
@@ -2474,34 +2458,32 @@
24742458
display@14f15000 {
24752459
compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
24762460
reg = <0 0x14f15000 0 0x1000>;
2477-
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>,
2478-
<&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>;
2479-
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
2461+
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>;
24802462
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>;
2463+
mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>,
2464+
<CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE>;
24812465
};
24822466

24832467
display@14f16000 {
24842468
compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
24852469
reg = <0 0x14f16000 0 0x1000>;
2486-
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>,
2487-
<&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>;
2488-
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
2470+
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>;
24892471
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>;
2472+
mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>,
2473+
<CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE>;
24902474
};
24912475

24922476
display@14f18000 {
24932477
compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp";
24942478
reg = <0 0x14f18000 0 0x1000>;
24952479
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>;
2496-
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
24972480
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>;
24982481
};
24992482

25002483
display@14f19000 {
25012484
compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp";
25022485
reg = <0 0x14f19000 0 0x1000>;
25032486
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>;
2504-
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
25052487
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>;
25062488
};
25072489

@@ -2524,6 +2506,7 @@
25242506
display@14f1d000 {
25252507
compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color";
25262508
reg = <0 0x14f1d000 0 0x1000>;
2509+
interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>;
25272510
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>;
25282511
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
25292512
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>;
@@ -2532,6 +2515,7 @@
25322515
display@14f1e000 {
25332516
compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color";
25342517
reg = <0 0x14f1e000 0 0x1000>;
2518+
interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>;
25352519
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>;
25362520
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
25372521
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>;
@@ -2558,6 +2542,7 @@
25582542
display@14f24000 {
25592543
compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
25602544
reg = <0 0x14f24000 0 0x1000>;
2545+
#dma-cells = <1>;
25612546
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>;
25622547
iommus = <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_WROT>;
25632548
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
@@ -2569,6 +2554,7 @@
25692554
display@14f25000 {
25702555
compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
25712556
reg = <0 0x14f25000 0 0x1000>;
2557+
#dma-cells = <1>;
25722558
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>;
25732559
iommus = <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_WROT>;
25742560
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;

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