@@ -251,17 +251,17 @@ static void timer_dma_init(void)
251
251
IRQx_enable (dma_wdata_irq );
252
252
253
253
/* RDATA Timer setup:
254
- * The counter is incremented at full SYSCLK rate.
254
+ * The counter is incremented at SAMPLECLK rate.
255
255
*
256
256
* Ch.2 (RDATA) is in PWM mode 1. It outputs O_TRUE for 400ns and then
257
257
* O_FALSE until the counter reloads. By changing the ARR via DMA we alter
258
258
* the time between (fixed-width) O_TRUE pulses, mimicking floppy drive
259
259
* timings. */
260
- tim_rdata -> psc = 0 ;
260
+ tim_rdata -> psc = ( SYSCLK_MHZ / SAMPLECLK_MHZ ) - 1 ;
261
261
tim_rdata -> ccmr1 = (TIM_CCMR1_CC2S (TIM_CCS_OUTPUT ) |
262
262
TIM_CCMR1_OC2M (TIM_OCM_PWM1 ));
263
263
tim_rdata -> ccer = TIM_CCER_CC2E | ((O_TRUE == 0 ) ? TIM_CCER_CC2P : 0 );
264
- tim_rdata -> ccr2 = sysclk_ns (400 );
264
+ tim_rdata -> ccr2 = sampleclk_ns (400 );
265
265
tim_rdata -> dier = TIM_DIER_UDE ;
266
266
tim_rdata -> cr2 = 0 ;
267
267
@@ -280,13 +280,13 @@ static void timer_dma_init(void)
280
280
DMA_CCR_EN );
281
281
282
282
/* WDATA Timer setup:
283
- * The counter runs from 0x0000-0xFFFF inclusive at full SYSCLK rate.
283
+ * The counter runs from 0x0000-0xFFFF inclusive at SAMPLECLK rate.
284
284
*
285
285
* Ch.1 (WDATA) is in Input Capture mode, sampling on every clock and with
286
286
* no input prescaling or filtering. Samples are captured on the falling
287
287
* edge of the input (CCxP=1). DMA is used to copy the sample into a ring
288
288
* buffer for batch processing in the DMA-completion ISR. */
289
- tim_wdata -> psc = 0 ;
289
+ tim_wdata -> psc = ( SYSCLK_MHZ / SAMPLECLK_MHZ ) - 1 ;
290
290
tim_wdata -> arr = 0xffff ;
291
291
tim_wdata -> ccmr1 = TIM_CCMR1_CC1S (TIM_CCS_INPUT_TI1 );
292
292
tim_wdata -> dier = TIM_DIER_CC1DE ;
@@ -407,10 +407,10 @@ static void wdata_start(void)
407
407
tim_wdata -> ccer = TIM_CCER_CC1E | TIM_CCER_CC1P ;
408
408
tim_wdata -> cr1 = TIM_CR1_CEN ;
409
409
410
- /* Find rotational start position of the write, in SYSCLK ticks. */
410
+ /* Find rotational start position of the write, in SAMPLECLK ticks. */
411
411
start_pos = max_t (int32_t , 0 , time_diff (index .prev_time , time_now ()));
412
412
start_pos %= drive .image -> stk_per_rev ;
413
- start_pos *= SYSCLK_MHZ / STK_MHZ ;
413
+ start_pos *= SAMPLECLK_MHZ / STK_MHZ ;
414
414
write = get_write (image , image -> wr_prod );
415
415
write -> start = start_pos ;
416
416
write -> track = drive_calc_track (& drive );
@@ -635,7 +635,7 @@ static void IRQ_rdata_dma(void)
635
635
/* Subtract current flux offset beyond the index. */
636
636
ticks -= image_ticks_since_index (drv -> image );
637
637
/* Calculate deadline for index timer. */
638
- ticks /= SYSCLK_MHZ /TIME_MHZ ;
638
+ ticks /= SAMPLECLK_MHZ /TIME_MHZ ;
639
639
timer_set (& index .timer , now + ticks );
640
640
}
641
641
0 commit comments