AT32F415: Run at 144MHz

Author: keirf

inc/decls.h

@@ -20,6 +20,7 @@
 #include "mcu/common.h"
 #if MCU == STM32F105
 #include "mcu/stm32f105_regs.h"
+#include "mcu/at32f415_regs.h"
 #include "mcu/stm32f105.h"
 #elif MCU == AT32F435
 #include "mcu/at32f435_regs.h"

inc/mcu/at32f415_regs.h

@@ -0,0 +1,34 @@
+/*
+ * at32f415_regs.h
+ * 
+ * Extra registers and features of the AT32F415 that we use, over and above
+ * the baseline features of the STM32F105.
+ * 
+ * Written & released by Keir Fraser <[email protected]>
+ * 
+ * This is free and unencumbered software released into the public domain.
+ * See the file COPYING for more details, or visit <http://unlicense.org>.
+ */
+
+#define RCC_CFGR_PLLMUL_18 ((uint32_t)0x20040000)
+#define RCC_CFGR_USBPSC_3  ((uint32_t)0x08400000)
+
+#define RCC_PLL (&rcc->cfgr2)
+#define RCC_PLL_PLLCFGEN  (1u<<31)
+#define RCC_PLL_FREF_MASK (7u<<24)
+#define RCC_PLL_FREF_8M   (2u<<24)
+
+static volatile uint32_t * const RCC_MISC2 = (uint32_t *)(RCC_BASE + 0x54);
+#define RCC_MISC2_AUTOSTEP_EN (3u<< 4)
+
+#define TIM_CR1_PMEN (1u<<10)
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "Linux"
+ * c-basic-offset: 4
+ * tab-width: 4
+ * indent-tabs-mode: nil
+ * End:
+ */

inc/mcu/at32f435.h

@@ -56,9 +56,9 @@ static USB_OTG usb_otg = (struct usb_otg *)USB_OTG_BASE;
 
 /* Clocks */
 #define SYSCLK_MHZ 288
-#define AHB_MHZ (SYSCLK_MHZ / 1)  /* 288MHz */
-#define APB1_MHZ (SYSCLK_MHZ / 2) /* 144MHz */
-#define APB2_MHZ (SYSCLK_MHZ / 2) /* 144MHz */
+#define AHB_MHZ    288
+#define APB1_MHZ   144
+#define APB2_MHZ   144
 
 /* GPIO */
 void gpio_set_af(GPIO gpio, unsigned int pin, unsigned int af);

inc/mcu/stm32f105.h

@@ -50,10 +50,12 @@ static USART usart3 = (struct usart *)USART3_BASE;
 static USB_OTG usb_otg = (struct usb_otg *)USB_OTG_BASE;
 
 /* Clocks */
-#define SYSCLK_MHZ 72
-#define AHB_MHZ (SYSCLK_MHZ / 1)  /* 72MHz */
-#define APB1_MHZ (SYSCLK_MHZ / 2) /* 36MHz */
-#define APB2_MHZ (SYSCLK_MHZ / 1) /* 72MHz */
+extern unsigned int sysclk_mhz;
+extern unsigned int apb1_mhz;
+#define SYSCLK_MHZ sysclk_mhz
+#define AHB_MHZ sysclk_mhz
+#define APB1_MHZ apb1_mhz
+#define APB2_MHZ 72
 
 #define SOFTIRQ_0 43
 #define SOFTIRQ_1 44

inc/mcu/stm32f105_regs.h

@@ -89,7 +89,8 @@ struct rcc {
 #define RCC_CFGR_PLLSRC_HSI  (0u<<16)
 #define RCC_CFGR_PLLSRC_PREDIV1 (1u<<16)
 #define RCC_CFGR_ADCPRE_DIV8 (3u<<14)
-#define RCC_CFGR_PPRE1_DIV2  (4u<<8)
+#define RCC_CFGR_APB2PSC_2   (4u<<11)
+#define RCC_CFGR_APB1PSC_2   (4u<< 8)
 #define RCC_CFGR_SWS_HSI     (0u<<2)
 #define RCC_CFGR_SWS_HSE     (1u<<2)
 #define RCC_CFGR_SWS_PLL     (2u<<2)

src/console.c

@@ -20,12 +20,14 @@
 #define usart_gpio gpioa
 #define usart_tx_pin 9
 #define usart_rx_pin 10
+#define PCLK (APB2_MHZ * 1000000)
 #else
 #define usart usart3
 #define USART_IRQ USART3_IRQ
 #define usart_gpio gpioc
 #define usart_tx_pin 10
 #define usart_rx_pin 11
+#define PCLK (APB1_MHZ * 1000000)
 #endif
 
 /* Normally flush to serial is asynchronously executed in a low-pri IRQ. */
@@ -147,7 +149,7 @@ void console_init(void)
 #endif
 
     /* BAUD, 8n1. */
-    usart->brr = (APB2_MHZ * 1000000) / BAUD;
+    usart->brr = PCLK / BAUD;
     usart->cr1 = USART_CR1_UE | USART_CR1_TE | USART_CR1_RE;
     usart->cr3 = 0;
 

src/display/lcd_stm32f105.c

@@ -74,6 +74,8 @@ const static struct i2c_cfg {
 #define SCL i2c_cfg->scl
 #define SDA i2c_cfg->sda
 
+#define PCLK_MHZ APB1_MHZ
+
 /* I2C error ISR. */
 #define I2C_ERROR_IRQ i2c_cfg->error_irq
 void IRQ_34(void) __attribute__((alias("IRQ_i2c_error")));
@@ -586,9 +588,9 @@ bool_t lcd_init(void)
 
     /* Standard Mode (100kHz) */
     i2c->cr1 = 0;
-    i2c->cr2 = I2C_CR2_FREQ(36);
-    i2c->ccr = I2C_CCR_CCR(180);
-    i2c->trise = 37;
+    i2c->cr2 = I2C_CR2_FREQ(PCLK_MHZ);
+    i2c->ccr = I2C_CCR_CCR(PCLK_MHZ*5);
+    i2c->trise = (PCLK_MHZ <= 62) ? PCLK_MHZ + 1 : 63;
     i2c->cr1 = I2C_CR1_PE;
 
     if (!reinit) {
@@ -1051,9 +1053,9 @@ static void oled_init_fast_mode(void)
     i2c->cr1 = 0;
 
     /* Fast Mode (400kHz). */
-    i2c->cr2 = I2C_CR2_FREQ(36);
-    i2c->ccr = I2C_CCR_FS | I2C_CCR_CCR(30);
-    i2c->trise = 12;
+    i2c->cr2 = I2C_CR2_FREQ(PCLK_MHZ);
+    i2c->ccr = I2C_CCR_FS | I2C_CCR_CCR(PCLK_MHZ*5/6);
+    i2c->trise = PCLK_MHZ*3/10 + 1;
     i2c->cr1 = I2C_CR1_PE;
     i2c->cr2 |= I2C_CR2_ITERREN;
 }

src/mcu_stm32f105.c

@@ -9,6 +9,9 @@
  * See the file COPYING for more details, or visit <http://unlicense.org>.
  */
 
+unsigned int sysclk_mhz = 72;
+unsigned int apb1_mhz = 36;
+
 bool_t is_artery_mcu;
 unsigned int flash_page_size = FLASH_PAGE_SIZE;
 unsigned int ram_kb = 64;
@@ -32,35 +35,56 @@ static void identify_mcu(void)
         ram_kb = 32;
         if (flash_kb == 128)
             flash_page_size = 1024;
+        sysclk_mhz = 144;
+        apb1_mhz = 72;
     }
 }
 
 static void clock_init(void)
 {
     /* Flash controller: reads require 2 wait states at 72MHz. */
-    flash->acr = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY(2);
+    flash->acr = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY(sysclk_mhz/32);
 
     /* Start up the external oscillator. */
     rcc->cr |= RCC_CR_HSEON;
     while (!(rcc->cr & RCC_CR_HSERDY))
         cpu_relax();
 
     /* PLLs, scalers, muxes. */
-    rcc->cfgr = (RCC_CFGR_PLLMUL(9) |        /* PLL = 9*8MHz = 72MHz */
-                 RCC_CFGR_PLLSRC_PREDIV1 |
-                 RCC_CFGR_ADCPRE_DIV8 |
-                 RCC_CFGR_PPRE1_DIV2);
+    if (is_artery_mcu) {
+        uint32_t rcc_pll = *RCC_PLL;
+        rcc_pll &= ~(RCC_PLL_PLLCFGEN | RCC_PLL_FREF_MASK);
+        rcc_pll |= RCC_PLL_FREF_8M;
+        *RCC_PLL = rcc_pll;
+        rcc->cfgr = (RCC_CFGR_PLLMUL_18 |        /* PLL = 18*8MHz = 144MHz */
+                     RCC_CFGR_USBPSC_3 |         /* USB = SYSCLK/3 = 48MHz */
+                     RCC_CFGR_PLLSRC_PREDIV1 |
+                     RCC_CFGR_ADCPRE_DIV8 |
+                     RCC_CFGR_APB2PSC_2 |        /* APB2 = SYSCLK/2 = 72MHz */
+                     RCC_CFGR_APB1PSC_2);        /* APB1 = SYSCLK/2 = 72MHz */
+    } else {
+        rcc->cfgr = (RCC_CFGR_PLLMUL(9) |        /* PLL = 9*8MHz = 72MHz */
+                     RCC_CFGR_PLLSRC_PREDIV1 |
+                     RCC_CFGR_ADCPRE_DIV8 |
+                     RCC_CFGR_APB1PSC_2);        /* APB1 = SYSCLK/2 = 36MHz */
+    }
 
     /* Enable and stabilise the PLL. */
     rcc->cr |= RCC_CR_PLLON;
     while (!(rcc->cr & RCC_CR_PLLRDY))
         cpu_relax();
 
+    if (is_artery_mcu)
+        *RCC_MISC2 |= RCC_MISC2_AUTOSTEP_EN;
+
     /* Switch to the externally-driven PLL for system clock. */
     rcc->cfgr |= RCC_CFGR_SW_PLL;
     while ((rcc->cfgr & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL)
         cpu_relax();
 
+    if (is_artery_mcu)
+        *RCC_MISC2 &= ~RCC_MISC2_AUTOSTEP_EN;
+
     /* Internal oscillator no longer needed. */
     rcc->cr &= ~RCC_CR_HSION;
 }

src/sd_spi.c

@@ -9,15 +9,9 @@
  * See the file COPYING for more details, or visit <http://unlicense.org>.
  */
 
-#if MCU == STM32F105
-/* Default Speed (25MHz). Closest we can get is 36Mhz/2 = 18MHz. */
-#define INIT_SPEED_DIV    SPI_BR_DIV128 /* ~281kHz (<400kHz) */
-#define DEFAULT_SPEED_DIV SPI_BR_DIV2   /* 18MHz */
-#elif MCU == AT32F435
-/* Default Speed (25MHz). Closest we can get is 144Mhz/8 = 18MHz. */
-#define INIT_SPEED_DIV    SPI_BR_DIV512 /* ~281kHz (<400kHz) */
-#define DEFAULT_SPEED_DIV SPI_BR_DIV8   /* 18MHz */
-#endif
+#define PCLK_MHZ APB1_MHZ
+#define INIT_SPEED_KHZ 400
+#define DEFAULT_SPEED_KHZ 25000
 #define SPI_PIN_SPEED _50MHz
 
 #if 0
@@ -270,8 +264,16 @@ static bool_t sd_inserted(void)
     return gpio_read_pin(gpioc, 9);
 }
 
-static void sd_spi_set_cr(uint32_t cr1, uint32_t br)
+static void sd_spi_set_cr(uint32_t cr1, unsigned int max_khz)
 {
+    /* Set the divisor to satisfy maximum communications frequency. */
+    uint32_t br = SPI_BR_DIV2;
+    unsigned int khz = (PCLK_MHZ * 1000) >> 1;
+    while (khz > max_khz) {
+        khz >>= 1;
+        br++;
+    }
+
     /* BR is called MDIV in AT32F435 documentation, and is extended by one
      * bit which resides in CR2. */
     spi->cr2 = (br & 8) << (8 - 3);    /* CR2[8]   := MDIV[3] */
@@ -314,7 +316,7 @@ static DSTATUS sd_disk_initialize(BYTE pdrv)
     cr1 = (SPI_CR1_MSTR | /* master */
            SPI_CR1_SSM | SPI_CR1_SSI | /* software NSS */
            SPI_CR1_SPE);
-    sd_spi_set_cr(cr1, INIT_SPEED_DIV);
+    sd_spi_set_cr(cr1, INIT_SPEED_KHZ);
 
     /* Drain SPI I/O. */
     spi_quiesce(spi);
@@ -396,7 +398,7 @@ static DSTATUS sd_disk_initialize(BYTE pdrv)
 
     if (!(status & STA_NOINIT)) {
         delay_us(10); /* XXX small delay here stops SPI getting stuck?? */
-        sd_spi_set_cr(cr1, DEFAULT_SPEED_DIV);
+        sd_spi_set_cr(cr1, DEFAULT_SPEED_KHZ);
         printk("SD Card configured\n");
         dump_cid_info();
     } else {