riscv: irq: Add trigger_irq function for clic

In a clic the mip register does not exist and software irq are triggered
in the clicintip register.

Signed-off-by: Greter Raffael <[email protected]>

Author: raffi-g

drivers/interrupt_controller/intc_nuclei_eclic.c

@@ -171,6 +171,14 @@ void riscv_clic_irq_priority_set(uint32_t irq, uint32_t pri, uint32_t flags)
 	ECLIC_CTRL[irq].INTATTR = intattr;
 }
 
+/**
+ * @brief Set pending bit of an interrupt
+ */
+void riscv_clic_irq_set_pending(uint32_t irq)
+{
+	ECLIC_CTRL[irq].INTIP.b.IP = 1;
+}
+
 static int nuclei_eclic_init(const struct device *dev)
 {
 	/* check hardware support required interrupt levels */

subsys/testsuite/include/zephyr/interrupt_util.h

@@ -166,6 +166,13 @@ static inline void trigger_irq(int irq)
 }
 
 #elif defined(CONFIG_RISCV)
+#if defined(CONFIG_NUCLEI_ECLIC)
+void riscv_clic_irq_set_pending(uint32_t irq);
+static inline void trigger_irq(int irq)
+{
+	riscv_clic_irq_set_pending(irq);
+}
+#else
 static inline void trigger_irq(int irq)
 {
 	uint32_t mip;
@@ -174,7 +181,7 @@ static inline void trigger_irq(int irq)
 			  : "=r" (mip)
 			  : "r" (1 << irq));
 }
-
+#endif
 #elif defined(CONFIG_XTENSA)
 static inline void trigger_irq(int irq)
 {