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1 parent 95a6c50 commit 97572d0Copy full SHA for 97572d0
llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -136,7 +136,7 @@ static cl::opt<bool> ForceLocalAssignment(
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"force-local-assignment",
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cl::desc("Force allocation order of local live ranges, such that "
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"shorter local live ranges will tend to be allocated first"),
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- cl::Hidden);
+ cl::init(false), cl::Hidden);
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static cl::opt<unsigned> SplitThresholdForRegWithHint(
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"split-threshold-for-reg-with-hint",
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