Auto select good flags

Rebase: 5708851

Author: jrbyrnes

llvm/include/llvm/CodeGen/RegAllocPriorityAdvisor.h

@@ -46,6 +46,7 @@ class RegAllocPriorityAdvisor {
   SlotIndexes *const Indexes;
   const bool RegClassPriorityTrumpsGlobalness;
   const bool ReverseLocalAssignment;
+  const bool ForceLocalAssignment;
 };
 
 class DefaultPriorityAdvisor : public RegAllocPriorityAdvisor {

llvm/include/llvm/CodeGen/TargetRegisterInfo.h

@@ -1020,6 +1020,8 @@ class LLVM_ABI TargetRegisterInfo : public MCRegisterInfo {
   /// (3) Bottom-up allocation is no longer guaranteed to optimally color.
   virtual bool reverseLocalAssignment() const { return false; }
 
+  virtual bool forceLocalAssignment() const { return false; }
+
   /// Allow the target to override the cost of using a callee-saved register for
   /// the first time. Default value of 0 means we will use a callee-saved
   /// register if it is available.

llvm/lib/CodeGen/RegAllocGreedy.cpp

@@ -132,11 +132,11 @@ static cl::opt<bool> GreedyReverseLocalAssignment(
              "shorter local live ranges will tend to be allocated first"),
     cl::Hidden);
 
-static cl::opt<bool> ForceLocalAssignment(
+static cl::opt<bool> GreedyForceLocalAssignment(
     "force-local-assignment",
     cl::desc("Force allocation order of local live ranges, such that "
              "shorter local live ranges will tend to be allocated first"),
-    cl::init(false), cl::Hidden);
+    cl::Hidden);
 
 static cl::opt<unsigned> SplitThresholdForRegWithHint(
     "split-threshold-for-reg-with-hint",
@@ -2898,6 +2898,10 @@ bool RAGreedy::run(MachineFunction &mf) {
                                ? GreedyReverseLocalAssignment
                                : TRI->reverseLocalAssignment();
 
+  ForceLocalAssignment = GreedyForceLocalAssignment.getNumOccurrences()
+                             ? GreedyForceLocalAssignment
+                             : TRI->forceLocalAssignment();
+
   ExtraInfo.emplace();
 
   EvictAdvisor = EvictProvider->getAdvisor(*MF, *this, MBFI, Loops);

llvm/lib/CodeGen/RegAllocGreedy.h

@@ -153,6 +153,7 @@ class LLVM_LIBRARY_VISIBILITY RAGreedy : public RegAllocBase,
     return RegClassPriorityTrumpsGlobalness;
   }
   bool getReverseLocalAssignment() const { return ReverseLocalAssignment; }
+  bool getForceLocalAssignment() const { return ForceLocalAssignment; }
   // end (interface to priority advisers)
 
 private:
@@ -286,6 +287,8 @@ class LLVM_LIBRARY_VISIBILITY RAGreedy : public RegAllocBase,
 
   bool ReverseLocalAssignment = false;
 
+  bool ForceLocalAssignment = false;
+
 public:
   RAGreedy(RequiredAnalyses &Analyses, const RegAllocFilterFunc F = nullptr);
 

llvm/lib/CodeGen/RegAllocPriorityAdvisor.cpp

@@ -215,4 +215,5 @@ RegAllocPriorityAdvisor::RegAllocPriorityAdvisor(const MachineFunction &MF,
       RegClassInfo(RA.getRegClassInfo()), Indexes(Indexes),
       RegClassPriorityTrumpsGlobalness(
           RA.getRegClassPriorityTrumpsGlobalness()),
-      ReverseLocalAssignment(RA.getReverseLocalAssignment()) {}
+      ReverseLocalAssignment(RA.getReverseLocalAssignment()),
+      ForceLocalAssignment(RA.getForceLocalAssignment()) {}

llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp

@@ -70,7 +70,7 @@ static cl::opt<bool>
     RematLiveThru("amdgpu-remat-livethru", cl::Hidden,
                   cl::desc("Rematerialize the LiveThru registers for the first "
                            "loop found in the code"),
-                  cl::init(true));
+                  cl::init(false));
 
 static cl::opt<bool> RematLiveIn(
     "amdgpu-remat-into", cl::Hidden,
@@ -516,8 +516,10 @@ SUnit *GCNSchedStrategy::pickNode(bool &IsTopNode) {
     if (IsXDL) {
       // FIXME: Hack since XDL is only actually occupying for 24 cycles with 8
       // pass MFMA.
-      if (Cycles > 2)
-        Cycles -= 2;
+      if (Cycles > 2) {
+        const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
+        Cycles -= ST.hasGFX950Insts() ? 2 : 1;
+      }
       XDLProcRes.reset();
       XDLProcRes.reserve(Cycles);
     } else if (IsALU) {
@@ -686,6 +688,19 @@ GCNMaxOccupancySchedStrategy::GCNMaxOccupancySchedStrategy(
   SchedStages.push_back(GCNSchedStageID::UnclusteredHighRPReschedule);
   SchedStages.push_back(GCNSchedStageID::ClusteredLowOccupancyReschedule);
   if (!DisableRemat) SchedStages.push_back(GCNSchedStageID::PreRARematerialize);
+
+  CI.clear();
+  CI.compute(*C->MF);
+
+  unsigned CycleCount = 0;
+  for (auto C : CI.toplevel_cycles()) {
+    ++CycleCount;
+  }
+  if (CycleCount >= 2) {
+    GCNTrackers = true;
+    RematLiveThru = true;
+  }
+
   GCNTrackers = GCNTrackers & !IsLegacyScheduler;
 }
 
@@ -1642,6 +1657,9 @@ bool PreRARematStage::initGCNSchedStage() {
   // need to be fixed if there is another pass after this pass.
   assert(!S.hasNextStage());
 
+  SIRegisterInfo *SRI = const_cast<SIRegisterInfo *>(
+      static_cast<const SIRegisterInfo *>(DAG.TRI));
+  SRI->setLocalAssignment(true);
   CI.clear();
   CI.compute(MF);
   PDT.recalculate(MF);
@@ -2834,8 +2852,10 @@ SUnit *GCNPostSchedStrategy::pickNode(bool &IsTopNode) {
     if (IsXDL) {
       // FIXME: Hack since XDL is only actually occupying for 24 cycles with 8
       // pass MFMA.
-      if (Cycles > 2)
-        Cycles -= 2;
+      if (Cycles > 2) {
+        const GCNSubtarget &ST = DAG->MF.getSubtarget<GCNSubtarget>();
+        Cycles -= ST.hasGFX950Insts() ? 2 : 1;
+      }
       XDLProcRes.reset();
       XDLProcRes.reserve(Cycles);
     } else if (IsALU) {

llvm/lib/Target/AMDGPU/GCNSchedStrategy.h

@@ -101,6 +101,8 @@ class GCNSchedStrategy : public GenericScheduler {
   // GCN RP Tracker for botttom-up scheduling
   mutable GCNUpwardRPTracker UpwardTracker;
 
+  MachineCycleInfo CI;
+
 public:
   // schedule() have seen register pressure over the critical limits and had to
   // track register pressure for actual scheduling heuristics.
@@ -672,24 +674,18 @@ class RematCandidates {
 
     std::set<RematCandidate> Cache;
 
-    // errs() << "HoistToDominator\n";
     for (auto RematInfo : RematMap) {
-      // errs() << "\nRemat Inst: "; RematInfo.first->dump();
       std::set<unsigned> HighRPs;
       SmallVector<MachineBasicBlock *> MBBs;
       for (auto R : RematInfo.second) {
         for (auto HRP : R.HighRPRegions) {
           HighRPs.insert(HRP);
         }
         MBBs.push_back(R.InsertPt->getParent());
-        // errs() << "Has remat point in: " <<
-        // printMBBReference(*R.InsertPt->getParent()) << "\n";
       }
 
       auto DomBlock = PDT->findNearestCommonDominator(iterator_range(MBBs));
       if (DomBlock && isReachableFrom(TargetBlock, DomBlock)) {
-        // errs() << "Found dom block: " << printMBBReference(*DomBlock) <<
-        // "\n";
         RematCandidate New(RematInfo.first, CI.getCycleDepth(DomBlock), HighRPs,
                            DomBlock->begin());
         Cache.insert(New);
@@ -700,37 +696,13 @@ class RematCandidates {
       }
     }
 
-    // errs() << "Condensed: " << Entries.size() << " into: " << Cache.size() <<
-    // "\n";
     Entries.clear();
     Entries = Cache;
     return true;
   }
 
   bool update(RematCandidate &RNew, const LiveIntervals *LIS) {
-    // errs() << "Update: "; RNew.Def->dump();
-    ////errs() << "Calling update for cand: ";
-    // RNew.Def->dump();
-    ////errs() << "With Regions: ";
-    // for (auto Regi : RNew.HighRPRegions) {
-    //   //errs() << Regi;
-    // }
-    ////errs() << "\n";
     auto Match = find_if(Entries, [RNew](const RematCandidate &R) {
-      if (R.Def == RNew.Def) {
-        ////errs() << "equal defs for cand match: \n";
-
-        // R.Def->dump();
-        ////errs() << "With Regions: ";
-        // for (auto Regi : R.HighRPRegions) {
-        //   //errs() << Regi;
-        // }
-        ////errs() << "\n";
-
-        ////errs() << "RNew parent: " << RNew.InsertPt->getParent()->getName()
-        ///<< "\n"; /errs() << "R parent: " <<
-        ///R.InsertPt->getParent()->getName() << "\n";
-      }
       return R.Def == RNew.Def &&
              RNew.InsertPt->getParent() == R.InsertPt->getParent();
     });
@@ -766,32 +738,21 @@ class RematCandidates {
 
   void resolveSameBlockUses(const MachineRegisterInfo *MRI,
                             const LiveIntervals *LIS) {
-    // errs() << "\nResolve Same Block uses";
     // We may have added remat candidates which are used by other remat
     // candidates -- be sure that we have correct insert points for this
     bool FixedPoint = false;
     while (!FixedPoint) {
-      // errs() << "Fixed Point iter\n";
-      //  //errs() << "Doling fixed point\n";
       FixedPoint = true;
       for (auto &RematEntry : Entries) {
 
         MachineInstr *RematInst = RematEntry.Def;
-        // errs() << "R: "; RematInst->dump();
-        // errs() << "For Regions: ";
-        // errs() << "\n";
         MachineBasicBlock::iterator RematPt = RematEntry.InsertPt;
-        // for (auto RematInst : RematEntry.second) {
-        //   //errs() << "Have Remat Inst: "; RematInst.first->dump();
-        // //errs() << "With Insert Point: " <<
-        // DAG.LIS->getInstructionIndex(*RematInst.second) << "\n";
         for (auto MO : RematInst->operands()) {
           if (!MO.isReg() || !MO.getReg() || !MO.readsReg())
             continue;
           auto UseReg = MO.getReg();
           if (!UseReg.isVirtual())
             continue;
-          // //errs() << "Found UseReg: " << printReg(UseReg) << "\n";
           for (MachineInstr &DefInst : MRI->def_instructions(UseReg)) {
 
             auto Match =

llvm/lib/Target/AMDGPU/SIRegisterInfo.h

@@ -44,6 +44,8 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
   bool isWave32;
   BitVector RegPressureIgnoredUnits;
 
+  bool ForceLocalAssignment = false;
+
   /// Sub reg indexes for getRegSplitParts.
   /// First index represents subreg size from 1 to 32 Half DWORDS.
   /// The inner vector is sorted by bit offset.
@@ -111,6 +113,10 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
     return 100;
   }
 
+  bool forceLocalAssignment() const override { return ForceLocalAssignment; }
+
+  void setLocalAssignment(bool Flag) { ForceLocalAssignment = Flag; }
+
   // When building a block VGPR load, we only really transfer a subset of the
   // registers in the block, based on a mask. Liveness analysis is not aware of
   // the mask, so it might consider that any register in the block is available