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EvenxfJiri Kosina
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HID: Intel-thc-hid: Intel-thc: Refine code comments
Align capitalization of the first characters for THC structure definition comments in header files. Signed-off-by: Even Xu <[email protected]> Signed-off-by: Jiri Kosina <[email protected]>
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drivers/hid/intel-thc-hid/intel-thc/intel-thc-dev.h

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -52,16 +52,16 @@ enum thc_int_type {
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* struct thc_device - THC private device struct
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* @thc_regmap: MMIO regmap structure for accessing THC registers
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* @mmio_addr: MMIO registers address
55-
* @thc_bus_lock: mutex locker for THC config
56-
* @port_type: port type of THC port instance
55+
* @thc_bus_lock: Mutex locker for THC config
56+
* @port_type: Port type of THC port instance
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* @pio_int_supported: PIO interrupt supported flag
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* @dma_ctx: DMA specific data
59-
* @write_complete_wait: signal event for DMA write complete
60-
* @swdma_complete_wait: signal event for SWDMA sequence complete
61-
* @write_done: bool value that indicates if DMA write is done
62-
* @swdma_done: bool value that indicates if SWDMA swquence is done
63-
* @perf_limit: the delay between read operation and write operation
64-
* @i2c_subip_regs: the copy of THC I2C sub-system registers for resuming restore
59+
* @write_complete_wait: Signal event for DMA write complete
60+
* @swdma_complete_wait: Signal event for SWDMA sequence complete
61+
* @write_done: Bool value that indicates if DMA write is done
62+
* @swdma_done: Bool value that indicates if SWDMA sequence is done
63+
* @perf_limit: The delay between read operation and write operation
64+
* @i2c_subip_regs: The copy of THC I2C sub-system registers for resuming restore
6565
*/
6666
struct thc_device {
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struct device *dev;

drivers/hid/intel-thc-hid/intel-thc/intel-thc-dma.h

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@
2727

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/**
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* THC DMA channels:
30-
* @THC_RXDMA1: legacy channel, reserved for raw data reading
30+
* @THC_RXDMA1: Legacy channel, reserved for raw data reading
3131
* @THC_RXDMA2: DMA to read HID data from touch device
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* @THC_TXDMA: DMA to write to touch device
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* @THC_SWDMA: SW triggered DMA to write and read from touch device
@@ -42,11 +42,11 @@ enum thc_dma_channel {
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4343
/**
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* THC DMA Physical Memory Descriptor (PRD)
45-
* @dest_addr: bit[53:0], destination address in system memory
46-
* @int_on_completion: bit[63], if set, thc will trigger interrupt to driver
47-
* @len: bit[87:64], length of this entry
48-
* @end_of_prd: bit[88], if set, this entry is last one of current PRD table
49-
* @hw_status: bit[90:89], hw status bits
45+
* @dest_addr: Bit[53:0], destination address in system memory
46+
* @int_on_completion: Bit[63], if set, thc will trigger interrupt to driver
47+
* @len: Bit[87:64], length of this entry
48+
* @end_of_prd: Bit[88], if set, this entry is last one of current PRD table
49+
* @hw_status: Bit[90:89], hardware status bits
5050
*/
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struct thc_prd_entry {
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u64 dest_addr : 54;
@@ -88,14 +88,14 @@ struct thc_prd_table {
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* struct thc_dma_configuration - THC DMA configure
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* @dma_channel: DMA channel for current DMA configuration
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* @prd_tbls_dma_handle: DMA buffer handle
91-
* @dir: direction of DMA for this config
91+
* @dir: Direction of DMA for this config
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* @prd_tbls: PRD tables for current DMA
93-
* @sgls: array of pointers to scatter-gather lists
94-
* @sgls_nent: actual number of entries per sg list
95-
* @prd_tbl_num: actual number of PRD tables
96-
* @max_packet_size: size of the buffer needed for 1 DMA message (1 PRD table)
93+
* @sgls: Array of pointers to scatter-gather lists
94+
* @sgls_nent: Actual number of entries per scatter-gather list
95+
* @prd_tbl_num: Actual number of PRD tables
96+
* @max_packet_size: Size of the buffer needed for 1 DMA message (1 PRD table)
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* @prd_base_addr_high: High 32bits memory address where stores PRD table
98-
* @prd_base_addr_low: low 32bits memory address where stores PRD table
98+
* @prd_base_addr_low: Low 32bits memory address where stores PRD table
9999
* @prd_cntrl: PRD control register value
100100
* @dma_cntrl: DMA control register value
101101
*/

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