27
27
28
28
/**
29
29
* THC DMA channels:
30
- * @THC_RXDMA1: legacy channel, reserved for raw data reading
30
+ * @THC_RXDMA1: Legacy channel, reserved for raw data reading
31
31
* @THC_RXDMA2: DMA to read HID data from touch device
32
32
* @THC_TXDMA: DMA to write to touch device
33
33
* @THC_SWDMA: SW triggered DMA to write and read from touch device
@@ -42,11 +42,11 @@ enum thc_dma_channel {
42
42
43
43
/**
44
44
* THC DMA Physical Memory Descriptor (PRD)
45
- * @dest_addr: bit [53:0], destination address in system memory
46
- * @int_on_completion: bit [63], if set, thc will trigger interrupt to driver
47
- * @len: bit [87:64], length of this entry
48
- * @end_of_prd: bit [88], if set, this entry is last one of current PRD table
49
- * @hw_status: bit [90:89], hw status bits
45
+ * @dest_addr: Bit [53:0], destination address in system memory
46
+ * @int_on_completion: Bit [63], if set, thc will trigger interrupt to driver
47
+ * @len: Bit [87:64], length of this entry
48
+ * @end_of_prd: Bit [88], if set, this entry is last one of current PRD table
49
+ * @hw_status: Bit [90:89], hardware status bits
50
50
*/
51
51
struct thc_prd_entry {
52
52
u64 dest_addr : 54 ;
@@ -88,14 +88,14 @@ struct thc_prd_table {
88
88
* struct thc_dma_configuration - THC DMA configure
89
89
* @dma_channel: DMA channel for current DMA configuration
90
90
* @prd_tbls_dma_handle: DMA buffer handle
91
- * @dir: direction of DMA for this config
91
+ * @dir: Direction of DMA for this config
92
92
* @prd_tbls: PRD tables for current DMA
93
- * @sgls: array of pointers to scatter-gather lists
94
- * @sgls_nent: actual number of entries per sg list
95
- * @prd_tbl_num: actual number of PRD tables
96
- * @max_packet_size: size of the buffer needed for 1 DMA message (1 PRD table)
93
+ * @sgls: Array of pointers to scatter-gather lists
94
+ * @sgls_nent: Actual number of entries per scatter-gather list
95
+ * @prd_tbl_num: Actual number of PRD tables
96
+ * @max_packet_size: Size of the buffer needed for 1 DMA message (1 PRD table)
97
97
* @prd_base_addr_high: High 32bits memory address where stores PRD table
98
- * @prd_base_addr_low: low 32bits memory address where stores PRD table
98
+ * @prd_base_addr_low: Low 32bits memory address where stores PRD table
99
99
* @prd_cntrl: PRD control register value
100
100
* @dma_cntrl: DMA control register value
101
101
*/
0 commit comments