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quic-kdybcioRob Clark
quic-kdybcio
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Rob Clark
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drm/msm: Offset MDSS HBB value by 13
The Adreno part of the driver exposes this value to userspace, and the SMEM data source also presents a x+13 value. Keep things coherent and make the value uniform across them. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/660961/ Signed-off-by: Rob Clark <[email protected]>
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‎drivers/gpu/drm/msm/msm_mdss.c

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -167,7 +167,7 @@ static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss)
167167
{
168168
const struct msm_mdss_data *data = msm_mdss->mdss_data;
169169
u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) |
170-
MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit);
170+
MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13);
171171

172172
if (data->ubwc_bank_spread)
173173
value |= MDSS_UBWC_STATIC_UBWC_BANK_SPREAD;
@@ -182,7 +182,7 @@ static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss)
182182
{
183183
const struct msm_mdss_data *data = msm_mdss->mdss_data;
184184
u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle & 0x1) |
185-
MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit);
185+
MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13);
186186

187187
if (data->macrotile_mode)
188188
value |= MDSS_UBWC_STATIC_MACROTILE_MODE;
@@ -200,7 +200,7 @@ static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss)
200200
{
201201
const struct msm_mdss_data *data = msm_mdss->mdss_data;
202202
u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) |
203-
MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit);
203+
MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13);
204204

205205
if (data->ubwc_bank_spread)
206206
value |= MDSS_UBWC_STATIC_UBWC_BANK_SPREAD;
@@ -277,9 +277,9 @@ static const struct msm_mdss_data *msm_mdss_generate_mdp5_mdss_data(struct msm_m
277277

278278
if (hw_rev == MDSS_HW_MSM8996 ||
279279
hw_rev == MDSS_HW_MSM8998)
280-
data->highest_bank_bit = 2;
280+
data->highest_bank_bit = 15;
281281
else
282-
data->highest_bank_bit = 1;
282+
data->highest_bank_bit = 14;
283283

284284
return data;
285285
}
@@ -593,13 +593,13 @@ static void mdss_remove(struct platform_device *pdev)
593593
static const struct msm_mdss_data msm8998_data = {
594594
.ubwc_enc_version = UBWC_1_0,
595595
.ubwc_dec_version = UBWC_1_0,
596-
.highest_bank_bit = 2,
596+
.highest_bank_bit = 15,
597597
.reg_bus_bw = 76800,
598598
};
599599

600600
static const struct msm_mdss_data qcm2290_data = {
601601
/* no UBWC */
602-
.highest_bank_bit = 0x2,
602+
.highest_bank_bit = 15,
603603
.reg_bus_bw = 76800,
604604
};
605605

@@ -608,7 +608,7 @@ static const struct msm_mdss_data sa8775p_data = {
608608
.ubwc_dec_version = UBWC_4_0,
609609
.ubwc_swizzle = 4,
610610
.ubwc_bank_spread = true,
611-
.highest_bank_bit = 0,
611+
.highest_bank_bit = 13,
612612
.macrotile_mode = true,
613613
.reg_bus_bw = 74000,
614614
};
@@ -618,7 +618,7 @@ static const struct msm_mdss_data sar2130p_data = {
618618
.ubwc_dec_version = UBWC_4_3,
619619
.ubwc_swizzle = 6,
620620
.ubwc_bank_spread = true,
621-
.highest_bank_bit = 0,
621+
.highest_bank_bit = 13,
622622
.macrotile_mode = 1,
623623
.reg_bus_bw = 74000,
624624
};
@@ -628,7 +628,7 @@ static const struct msm_mdss_data sc7180_data = {
628628
.ubwc_dec_version = UBWC_2_0,
629629
.ubwc_swizzle = 6,
630630
.ubwc_bank_spread = true,
631-
.highest_bank_bit = 0x1,
631+
.highest_bank_bit = 14,
632632
.reg_bus_bw = 76800,
633633
};
634634

@@ -637,15 +637,15 @@ static const struct msm_mdss_data sc7280_data = {
637637
.ubwc_dec_version = UBWC_4_0,
638638
.ubwc_swizzle = 6,
639639
.ubwc_bank_spread = true,
640-
.highest_bank_bit = 1,
640+
.highest_bank_bit = 14,
641641
.macrotile_mode = true,
642642
.reg_bus_bw = 74000,
643643
};
644644

645645
static const struct msm_mdss_data sc8180x_data = {
646646
.ubwc_enc_version = UBWC_3_0,
647647
.ubwc_dec_version = UBWC_3_0,
648-
.highest_bank_bit = 3,
648+
.highest_bank_bit = 16,
649649
.macrotile_mode = true,
650650
.reg_bus_bw = 76800,
651651
};
@@ -655,22 +655,22 @@ static const struct msm_mdss_data sc8280xp_data = {
655655
.ubwc_dec_version = UBWC_4_0,
656656
.ubwc_swizzle = 6,
657657
.ubwc_bank_spread = true,
658-
.highest_bank_bit = 3,
658+
.highest_bank_bit = 16,
659659
.macrotile_mode = true,
660660
.reg_bus_bw = 76800,
661661
};
662662

663663
static const struct msm_mdss_data sdm670_data = {
664664
.ubwc_enc_version = UBWC_2_0,
665665
.ubwc_dec_version = UBWC_2_0,
666-
.highest_bank_bit = 1,
666+
.highest_bank_bit = 14,
667667
.reg_bus_bw = 76800,
668668
};
669669

670670
static const struct msm_mdss_data sdm845_data = {
671671
.ubwc_enc_version = UBWC_2_0,
672672
.ubwc_dec_version = UBWC_2_0,
673-
.highest_bank_bit = 2,
673+
.highest_bank_bit = 15,
674674
.reg_bus_bw = 76800,
675675
};
676676

@@ -679,21 +679,21 @@ static const struct msm_mdss_data sm6350_data = {
679679
.ubwc_dec_version = UBWC_2_0,
680680
.ubwc_swizzle = 6,
681681
.ubwc_bank_spread = true,
682-
.highest_bank_bit = 1,
682+
.highest_bank_bit = 14,
683683
.reg_bus_bw = 76800,
684684
};
685685

686686
static const struct msm_mdss_data sm7150_data = {
687687
.ubwc_enc_version = UBWC_2_0,
688688
.ubwc_dec_version = UBWC_2_0,
689-
.highest_bank_bit = 1,
689+
.highest_bank_bit = 14,
690690
.reg_bus_bw = 76800,
691691
};
692692

693693
static const struct msm_mdss_data sm8150_data = {
694694
.ubwc_enc_version = UBWC_3_0,
695695
.ubwc_dec_version = UBWC_3_0,
696-
.highest_bank_bit = 2,
696+
.highest_bank_bit = 15,
697697
.reg_bus_bw = 76800,
698698
};
699699

@@ -702,21 +702,21 @@ static const struct msm_mdss_data sm6115_data = {
702702
.ubwc_dec_version = UBWC_2_0,
703703
.ubwc_swizzle = 7,
704704
.ubwc_bank_spread = true,
705-
.highest_bank_bit = 0x1,
705+
.highest_bank_bit = 14,
706706
.reg_bus_bw = 76800,
707707
};
708708

709709
static const struct msm_mdss_data sm6125_data = {
710710
.ubwc_enc_version = UBWC_1_0,
711711
.ubwc_dec_version = UBWC_3_0,
712712
.ubwc_swizzle = 1,
713-
.highest_bank_bit = 1,
713+
.highest_bank_bit = 14,
714714
};
715715

716716
static const struct msm_mdss_data sm6150_data = {
717717
.ubwc_enc_version = UBWC_2_0,
718718
.ubwc_dec_version = UBWC_2_0,
719-
.highest_bank_bit = 1,
719+
.highest_bank_bit = 14,
720720
.reg_bus_bw = 76800,
721721
};
722722

@@ -726,7 +726,7 @@ static const struct msm_mdss_data sm8250_data = {
726726
.ubwc_swizzle = 6,
727727
.ubwc_bank_spread = true,
728728
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
729-
.highest_bank_bit = 3,
729+
.highest_bank_bit = 16,
730730
.macrotile_mode = true,
731731
.reg_bus_bw = 76800,
732732
};
@@ -737,7 +737,7 @@ static const struct msm_mdss_data sm8350_data = {
737737
.ubwc_swizzle = 6,
738738
.ubwc_bank_spread = true,
739739
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
740-
.highest_bank_bit = 3,
740+
.highest_bank_bit = 16,
741741
.macrotile_mode = true,
742742
.reg_bus_bw = 74000,
743743
};
@@ -748,7 +748,7 @@ static const struct msm_mdss_data sm8550_data = {
748748
.ubwc_swizzle = 6,
749749
.ubwc_bank_spread = true,
750750
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
751-
.highest_bank_bit = 3,
751+
.highest_bank_bit = 16,
752752
.macrotile_mode = true,
753753
.reg_bus_bw = 57000,
754754
};
@@ -759,7 +759,7 @@ static const struct msm_mdss_data sm8750_data = {
759759
.ubwc_swizzle = 6,
760760
.ubwc_bank_spread = true,
761761
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
762-
.highest_bank_bit = 3,
762+
.highest_bank_bit = 16,
763763
.macrotile_mode = true,
764764
.reg_bus_bw = 57000,
765765
};
@@ -770,7 +770,7 @@ static const struct msm_mdss_data x1e80100_data = {
770770
.ubwc_swizzle = 6,
771771
.ubwc_bank_spread = true,
772772
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
773-
.highest_bank_bit = 3,
773+
.highest_bank_bit = 16,
774774
.macrotile_mode = true,
775775
/* TODO: Add reg_bus_bw with real value */
776776
};

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