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Commit 2284cca

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Russell King (Oracle)kuba-moo
authored andcommitted
net: stmmac: ingenic: simplify x2000 mac_set_mode()
As per the previous commit, we have validated that the phy_intf_sel value is one that is permissible for this SoC, so there is no need to handle invalid PHY interface modes. We can also apply the other configuration based upon the phy_intf_sel value rather than the PHY interface mode. Reviewed-by: Maxime Chevallier <[email protected]> Signed-off-by: Russell King (Oracle) <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
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drivers/net/ethernet/stmicro/stmmac/dwmac-ingenic.c

Lines changed: 7 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -122,39 +122,25 @@ static int x2000_mac_set_mode(struct plat_stmmacenet_data *plat_dat,
122122
struct ingenic_mac *mac = plat_dat->bsp_priv;
123123
unsigned int val;
124124

125-
switch (plat_dat->phy_interface) {
126-
case PHY_INTERFACE_MODE_RMII:
127-
val = FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_ORIGIN) |
128-
FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_ORIGIN);
129-
break;
130-
131-
case PHY_INTERFACE_MODE_RGMII:
132-
case PHY_INTERFACE_MODE_RGMII_ID:
133-
case PHY_INTERFACE_MODE_RGMII_TXID:
134-
case PHY_INTERFACE_MODE_RGMII_RXID:
135-
val = 0;
125+
val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, phy_intf_sel);
126+
127+
if (phy_intf_sel == PHY_INTF_SEL_RMII) {
128+
val |= FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_ORIGIN) |
129+
FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_ORIGIN);
130+
} else if (phy_intf_sel == PHY_INTF_SEL_RGMII) {
136131
if (mac->tx_delay == 0)
137132
val |= FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_ORIGIN);
138133
else
139134
val |= FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_DELAY) |
140-
FIELD_PREP(MACPHYC_TX_DELAY_MASK, (mac->tx_delay + 9750) / 19500 - 1);
135+
FIELD_PREP(MACPHYC_TX_DELAY_MASK, (mac->tx_delay + 9750) / 19500 - 1);
141136

142137
if (mac->rx_delay == 0)
143138
val |= FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_ORIGIN);
144139
else
145140
val |= FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_DELAY) |
146141
FIELD_PREP(MACPHYC_RX_DELAY_MASK, (mac->rx_delay + 9750) / 19500 - 1);
147-
148-
break;
149-
150-
default:
151-
dev_err(mac->dev, "Unsupported interface %s\n",
152-
phy_modes(plat_dat->phy_interface));
153-
return -EINVAL;
154142
}
155143

156-
val |= FIELD_PREP(MACPHYC_PHY_INFT_MASK, phy_intf_sel);
157-
158144
/* Update MAC PHY control register */
159145
return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, val);
160146
}

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