Skip to content

Commit 240ef19

Browse files
sjakhadecdnsvinodkoul
authored andcommitted
phy: cadence-torrent: Add PCIe multilink configuration for 100 MHz refclk
Add register sequences to support PCIe multilink configuration for 100MHz reference clock. Maximum two PCIe links are supported. Signed-off-by: Swapnil Jakhade <[email protected]> Signed-off-by: Siddharth Vadapalli <[email protected]> Reviewed-by: Roger Quadros <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
1 parent 47311ea commit 240ef19

File tree

1 file changed

+129
-1
lines changed

1 file changed

+129
-1
lines changed

drivers/phy/cadence/phy-cadence-torrent.c

Lines changed: 129 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -197,13 +197,15 @@
197197
#define RX_SDCAL1_INIT_TMR 0x004CU
198198
#define RX_SDCAL1_ITER_TMR 0x004DU
199199
#define RX_CDRLF_CNFG 0x0080U
200+
#define RX_CDRLF_CNFG2 0x0081U
200201
#define RX_CDRLF_CNFG3 0x0082U
201202
#define RX_SIGDET_HL_FILT_TMR 0x0090U
202203
#define RX_REE_GCSM1_CTRL 0x0108U
203204
#define RX_REE_GCSM1_EQENM_PH1 0x0109U
204205
#define RX_REE_GCSM1_EQENM_PH2 0x010AU
205206
#define RX_REE_GCSM2_CTRL 0x0110U
206207
#define RX_REE_PERGCSM_CTRL 0x0118U
208+
#define RX_REE_PEAK_UTHR 0x0142U
207209
#define RX_REE_ATTEN_THR 0x0149U
208210
#define RX_REE_TAP1_CLIP 0x0171U
209211
#define RX_REE_TAP2TON_CLIP 0x0172U
@@ -212,6 +214,7 @@
212214
#define RX_DIAG_DFE_CTRL 0x01E0U
213215
#define RX_DIAG_DFE_AMP_TUNE_2 0x01E2U
214216
#define RX_DIAG_DFE_AMP_TUNE_3 0x01E3U
217+
#define RX_DIAG_REE_DAC_CTRL 0x01E4U
215218
#define RX_DIAG_NQST_CTRL 0x01E5U
216219
#define RX_DIAG_SIGDET_TUNE 0x01E8U
217220
#define RX_DIAG_PI_RATE 0x01F4U
@@ -3131,6 +3134,101 @@ static void cdns_torrent_phy_remove(struct platform_device *pdev)
31313134
cdns_torrent_clk_cleanup(cdns_phy);
31323135
}
31333136

3137+
/* Multi link PCIe configuration */
3138+
static const struct cdns_reg_pairs ml_pcie_link_cmn_regs[] = {
3139+
{0x0002, PHY_PLL_CFG},
3140+
{0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}
3141+
};
3142+
3143+
static const struct cdns_reg_pairs ml_pcie_xcvr_diag_ln_regs[] = {
3144+
{0x0100, XCVR_DIAG_HSCLK_SEL},
3145+
{0x0001, XCVR_DIAG_HSCLK_DIV},
3146+
{0x0812, XCVR_DIAG_PLLDRC_CTRL}
3147+
};
3148+
3149+
static const struct cdns_torrent_vals ml_pcie_link_cmn_vals = {
3150+
.reg_pairs = ml_pcie_link_cmn_regs,
3151+
.num_regs = ARRAY_SIZE(ml_pcie_link_cmn_regs),
3152+
};
3153+
3154+
static const struct cdns_torrent_vals ml_pcie_xcvr_diag_ln_vals = {
3155+
.reg_pairs = ml_pcie_xcvr_diag_ln_regs,
3156+
.num_regs = ARRAY_SIZE(ml_pcie_xcvr_diag_ln_regs),
3157+
};
3158+
3159+
/* Multi link PCIe, 100 MHz Ref clk, no SSC */
3160+
static const struct cdns_reg_pairs ml_pcie_100_no_ssc_cmn_regs[] = {
3161+
{0x0003, CMN_PLL0_VCOCAL_TCTRL},
3162+
{0x0003, CMN_PLL1_VCOCAL_TCTRL}
3163+
};
3164+
3165+
static const struct cdns_reg_pairs ml_pcie_100_no_ssc_rx_ln_regs[] = {
3166+
{0x0019, RX_REE_TAP1_CLIP},
3167+
{0x0019, RX_REE_TAP2TON_CLIP},
3168+
{0x0008, RX_REE_PEAK_UTHR},
3169+
{0x018E, RX_CDRLF_CNFG},
3170+
{0x2E33, RX_CDRLF_CNFG2},
3171+
{0x0001, RX_DIAG_ACYA},
3172+
{0x0C21, RX_DIAG_DFE_AMP_TUNE_2},
3173+
{0x0002, RX_DIAG_DFE_AMP_TUNE_3},
3174+
{0x0005, RX_DIAG_REE_DAC_CTRL}
3175+
};
3176+
3177+
static const struct cdns_torrent_vals ml_pcie_100_no_ssc_cmn_vals = {
3178+
.reg_pairs = ml_pcie_100_no_ssc_cmn_regs,
3179+
.num_regs = ARRAY_SIZE(ml_pcie_100_no_ssc_cmn_regs),
3180+
};
3181+
3182+
static const struct cdns_torrent_vals ml_pcie_100_no_ssc_rx_ln_vals = {
3183+
.reg_pairs = ml_pcie_100_no_ssc_rx_ln_regs,
3184+
.num_regs = ARRAY_SIZE(ml_pcie_100_no_ssc_rx_ln_regs),
3185+
};
3186+
3187+
/* Multi link PCIe, 100 MHz Ref clk, internal SSC */
3188+
static const struct cdns_reg_pairs ml_pcie_100_int_ssc_cmn_regs[] = {
3189+
{0x0004, CMN_PLL0_DSM_DIAG_M0},
3190+
{0x0004, CMN_PLL1_DSM_DIAG_M0},
3191+
{0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3192+
{0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3193+
{0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3194+
{0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3195+
{0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3196+
{0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3197+
{0x0064, CMN_PLL0_INTDIV_M0},
3198+
{0x0050, CMN_PLL1_INTDIV_M0},
3199+
{0x0002, CMN_PLL0_FRACDIVH_M0},
3200+
{0x0002, CMN_PLL1_FRACDIVH_M0},
3201+
{0x0044, CMN_PLL0_HIGH_THR_M0},
3202+
{0x0036, CMN_PLL1_HIGH_THR_M0},
3203+
{0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3204+
{0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3205+
{0x0001, CMN_PLL0_SS_CTRL1_M0},
3206+
{0x0001, CMN_PLL1_SS_CTRL1_M0},
3207+
{0x011B, CMN_PLL0_SS_CTRL2_M0},
3208+
{0x011B, CMN_PLL1_SS_CTRL2_M0},
3209+
{0x006E, CMN_PLL0_SS_CTRL3_M0},
3210+
{0x0058, CMN_PLL1_SS_CTRL3_M0},
3211+
{0x000E, CMN_PLL0_SS_CTRL4_M0},
3212+
{0x0012, CMN_PLL1_SS_CTRL4_M0},
3213+
{0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3214+
{0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3215+
{0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3216+
{0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3217+
{0x0003, CMN_PLL0_VCOCAL_TCTRL},
3218+
{0x0003, CMN_PLL1_VCOCAL_TCTRL},
3219+
{0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3220+
{0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3221+
{0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3222+
{0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3223+
{0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3224+
{0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
3225+
};
3226+
3227+
static const struct cdns_torrent_vals ml_pcie_100_int_ssc_cmn_vals = {
3228+
.reg_pairs = ml_pcie_100_int_ssc_cmn_regs,
3229+
.num_regs = ARRAY_SIZE(ml_pcie_100_int_ssc_cmn_regs),
3230+
};
3231+
31343232
/* SGMII and QSGMII link configuration */
31353233
static const struct cdns_reg_pairs sgmii_qsgmii_link_cmn_regs[] = {
31363234
{0x0002, PHY_PLL_CFG}
@@ -4531,7 +4629,7 @@ static const struct cdns_torrent_vals sl_sgmii_xcvr_diag_ln_vals = {
45314629
.num_regs = ARRAY_SIZE(sl_sgmii_xcvr_diag_ln_regs),
45324630
};
45334631

4534-
/* Multi link PCIe, 100 MHz Ref clk, internal SSC */
4632+
/* For PCIe (with some other protocol), 100 MHz Ref clk, internal SSC */
45354633
static const struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = {
45364634
{0x0004, CMN_PLL0_DSM_DIAG_M0},
45374635
{0x0004, CMN_PLL0_DSM_DIAG_M1},
@@ -4670,6 +4768,7 @@ static const struct cdns_torrent_vals_entry link_cmn_vals_entries[] = {
46704768
{CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_USB), &usb_dp_link_cmn_vals},
46714769

46724770
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_NONE), NULL},
4771+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_PCIE), &ml_pcie_link_cmn_vals},
46734772
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_SGMII), &pcie_sgmii_link_cmn_vals},
46744773
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_QSGMII), &pcie_sgmii_link_cmn_vals},
46754774
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USB), &pcie_usb_link_cmn_vals},
@@ -4706,6 +4805,7 @@ static const struct cdns_torrent_vals_entry xcvr_diag_vals_entries[] = {
47064805
{CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_USB), &dp_usb_xcvr_diag_ln_vals},
47074806

47084807
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_NONE), NULL},
4808+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_PCIE), &ml_pcie_xcvr_diag_ln_vals},
47094809
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_SGMII), &pcie_sgmii_xcvr_diag_ln_vals},
47104810
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_QSGMII), &pcie_sgmii_xcvr_diag_ln_vals},
47114811
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USB), &pcie_usb_xcvr_diag_ln_vals},
@@ -4756,6 +4856,10 @@ static const struct cdns_torrent_vals_entry cmn_vals_entries[] = {
47564856
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
47574857
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &sl_pcie_100_int_ssc_cmn_vals},
47584858

4859+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), &ml_pcie_100_no_ssc_cmn_vals},
4860+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), &ml_pcie_100_no_ssc_cmn_vals},
4861+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), &ml_pcie_100_int_ssc_cmn_vals},
4862+
47594863
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_cmn_vals},
47604864
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals},
47614865
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},
@@ -4838,6 +4942,10 @@ static const struct cdns_torrent_vals_entry cdns_tx_ln_vals_entries[] = {
48384942
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
48394943
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL},
48404944

4945+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), NULL},
4946+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), NULL},
4947+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), NULL},
4948+
48414949
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL},
48424950
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL},
48434951
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL},
@@ -4920,6 +5028,10 @@ static const struct cdns_torrent_vals_entry cdns_rx_ln_vals_entries[] = {
49205028
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
49215029
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
49225030

5031+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), &ml_pcie_100_no_ssc_rx_ln_vals},
5032+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), &ml_pcie_100_no_ssc_rx_ln_vals},
5033+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), &ml_pcie_100_no_ssc_rx_ln_vals},
5034+
49235035
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
49245036
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
49255037
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
@@ -5038,6 +5150,10 @@ static const struct cdns_torrent_vals_entry ti_tx_ln_vals_entries[] = {
50385150
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
50395151
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL},
50405152

5153+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), NULL},
5154+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), NULL},
5155+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), NULL},
5156+
50415157
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL},
50425158
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL},
50435159
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL},
@@ -5154,6 +5270,10 @@ static const struct cdns_torrent_vals_entry ti_j7200_cmn_vals_entries[] = {
51545270
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
51555271
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &sl_pcie_100_int_ssc_cmn_vals},
51565272

5273+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), &ml_pcie_100_no_ssc_cmn_vals},
5274+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), &ml_pcie_100_no_ssc_cmn_vals},
5275+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), &ml_pcie_100_int_ssc_cmn_vals},
5276+
51575277
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_cmn_vals},
51585278
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals},
51595279
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},
@@ -5236,6 +5356,10 @@ static const struct cdns_torrent_vals_entry ti_j7200_tx_ln_vals_entries[] = {
52365356
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
52375357
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL},
52385358

5359+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), NULL},
5360+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), NULL},
5361+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), NULL},
5362+
52395363
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL},
52405364
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL},
52415365
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL},
@@ -5318,6 +5442,10 @@ static const struct cdns_torrent_vals_entry ti_j7200_rx_ln_vals_entries[] = {
53185442
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
53195443
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
53205444

5445+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
5446+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
5447+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
5448+
53215449
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
53225450
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
53235451
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},

0 commit comments

Comments
 (0)