@@ -28,7 +28,8 @@ bool skip_all_tests = true;
2828
2929#if defined(ENABLE_ATOMICS_TESTS ) && \
3030 defined(__BPF_FEATURE_ADDR_SPACE_CAST ) && \
31- (defined(__TARGET_ARCH_arm64 ) || defined(__TARGET_ARCH_x86 ))
31+ (defined(__TARGET_ARCH_arm64 ) || defined(__TARGET_ARCH_x86 ) || \
32+ (defined(__TARGET_ARCH_riscv ) && __riscv_xlen == 64 ))
3233bool skip_lacq_srel_tests __attribute((__section__ (".data" ))) = false;
3334#else
3435bool skip_lacq_srel_tests = true;
@@ -314,7 +315,8 @@ int load_acquire(const void *ctx)
314315{
315316#if defined(ENABLE_ATOMICS_TESTS ) && \
316317 defined(__BPF_FEATURE_ADDR_SPACE_CAST ) && \
317- (defined(__TARGET_ARCH_arm64 ) || defined(__TARGET_ARCH_x86 ))
318+ (defined(__TARGET_ARCH_arm64 ) || defined(__TARGET_ARCH_x86 ) || \
319+ (defined(__TARGET_ARCH_riscv ) && __riscv_xlen == 64 ))
318320
319321#define LOAD_ACQUIRE_ARENA (SIZEOP , SIZE , SRC , DST ) \
320322 { asm volatile ( \
@@ -365,7 +367,8 @@ int store_release(const void *ctx)
365367{
366368#if defined(ENABLE_ATOMICS_TESTS ) && \
367369 defined(__BPF_FEATURE_ADDR_SPACE_CAST ) && \
368- (defined(__TARGET_ARCH_arm64 ) || defined(__TARGET_ARCH_x86 ))
370+ (defined(__TARGET_ARCH_arm64 ) || defined(__TARGET_ARCH_x86 ) || \
371+ (defined(__TARGET_ARCH_riscv ) && __riscv_xlen == 64 ))
369372
370373#define STORE_RELEASE_ARENA (SIZEOP , DST , VAL ) \
371374 { asm volatile ( \
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