Skip to content

Commit 2a5cebd

Browse files
bebarinobebarino
committed
Merge tag 'samsung-clk-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
Pull Samsung SoC clk driver updates from Krzysztof Kozlowski: - Fixes for clock topology on Google GS101 - Add HSI2 clk controller on ExynosAutov920 - Minor comment fix for Exynos850 clk driver * tag 'samsung-clk-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: clk: samsung: exynosautov920: add block hsi2 clock support dt-bindings: clock: exynosautov920: add hsi2 clock definitions dt-bindings: clock: exynosautov920: sort clock definitions clk: samsung: exynos850: fix a comment clk: samsung: gs101: fix alternate mout_hsi0_usb20_ref parent clock clk: samsung: gs101: fix CLK_DOUT_CMU_G3D_BUSD
2 parents 19272b3 + 2d539f3 commit 2a5cebd

File tree

5 files changed

+115
-9
lines changed

5 files changed

+115
-9
lines changed

‎Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml‎

Lines changed: 31 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -32,23 +32,24 @@ description: |
3232
properties:
3333
compatible:
3434
enum:
35-
- samsung,exynosautov920-cmu-top
3635
- samsung,exynosautov920-cmu-cpucl0
3736
- samsung,exynosautov920-cmu-cpucl1
3837
- samsung,exynosautov920-cmu-cpucl2
39-
- samsung,exynosautov920-cmu-peric0
40-
- samsung,exynosautov920-cmu-peric1
41-
- samsung,exynosautov920-cmu-misc
4238
- samsung,exynosautov920-cmu-hsi0
4339
- samsung,exynosautov920-cmu-hsi1
40+
- samsung,exynosautov920-cmu-hsi2
41+
- samsung,exynosautov920-cmu-misc
42+
- samsung,exynosautov920-cmu-peric0
43+
- samsung,exynosautov920-cmu-peric1
44+
- samsung,exynosautov920-cmu-top
4445

4546
clocks:
4647
minItems: 1
47-
maxItems: 4
48+
maxItems: 5
4849

4950
clock-names:
5051
minItems: 1
51-
maxItems: 4
52+
maxItems: 5
5253

5354
"#clock-cells":
5455
const: 1
@@ -201,6 +202,30 @@ allOf:
201202
- const: usbdrd
202203
- const: mmc_card
203204

205+
- if:
206+
properties:
207+
compatible:
208+
contains:
209+
const: samsung,exynosautov920-cmu-hsi2
210+
211+
then:
212+
properties:
213+
clocks:
214+
items:
215+
- description: External reference clock (38.4 MHz)
216+
- description: CMU_HSI2 NOC clock (from CMU_TOP)
217+
- description: CMU_HSI2 NOC UFS clock (from CMU_TOP)
218+
- description: CMU_HSI2 UFS EMBD clock (from CMU_TOP)
219+
- description: CMU_HSI2 ETHERNET clock (from CMU_TOP)
220+
221+
clock-names:
222+
items:
223+
- const: oscclk
224+
- const: noc
225+
- const: ufs
226+
- const: embd
227+
- const: ethernet
228+
204229
required:
205230
- compatible
206231
- "#clock-cells"

‎drivers/clk/samsung/clk-exynos850.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1360,7 +1360,7 @@ static const unsigned long cpucl1_clk_regs[] __initconst = {
13601360
CLK_CON_GAT_GATE_CLK_CPUCL1_CPU,
13611361
};
13621362

1363-
/* List of parent clocks for Muxes in CMU_CPUCL0 */
1363+
/* List of parent clocks for Muxes in CMU_CPUCL1 */
13641364
PNAME(mout_pll_cpucl1_p) = { "oscclk", "fout_cpucl1_pll" };
13651365
PNAME(mout_cpucl1_switch_user_p) = { "oscclk", "dout_cpucl1_switch" };
13661366
PNAME(mout_cpucl1_dbg_user_p) = { "oscclk", "dout_cpucl1_dbg" };

‎drivers/clk/samsung/clk-exynosautov920.c‎

Lines changed: 72 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@
2626
#define CLKS_NR_MISC (CLK_DOUT_MISC_OSC_DIV2 + 1)
2727
#define CLKS_NR_HSI0 (CLK_DOUT_HSI0_PCIE_APB + 1)
2828
#define CLKS_NR_HSI1 (CLK_MOUT_HSI1_USBDRD + 1)
29+
#define CLKS_NR_HSI2 (CLK_DOUT_HSI2_ETHERNET_PTP + 1)
2930

3031
/* ---- CMU_TOP ------------------------------------------------------------ */
3132

@@ -1752,6 +1753,74 @@ static const struct samsung_cmu_info hsi1_cmu_info __initconst = {
17521753
.clk_name = "noc",
17531754
};
17541755

1756+
/* ---- CMU_HSI2 --------------------------------------------------------- */
1757+
1758+
/* Register Offset definitions for CMU_HSI2 (0x16b00000) */
1759+
#define PLL_LOCKTIME_PLL_ETH 0x0
1760+
#define PLL_CON3_PLL_ETH 0x10c
1761+
#define PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER 0x600
1762+
#define PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER 0x610
1763+
#define PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x630
1764+
#define CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET 0x1000
1765+
#define CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET 0x1800
1766+
#define CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP 0x1804
1767+
1768+
static const unsigned long hsi2_clk_regs[] __initconst = {
1769+
PLL_LOCKTIME_PLL_ETH,
1770+
PLL_CON3_PLL_ETH,
1771+
PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER,
1772+
PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER,
1773+
PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER,
1774+
CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET,
1775+
CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET,
1776+
CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP,
1777+
};
1778+
1779+
static const struct samsung_pll_clock hsi2_pll_clks[] __initconst = {
1780+
/* CMU_HSI2_PLL */
1781+
PLL(pll_531x, FOUT_PLL_ETH, "fout_pll_eth", "oscclk",
1782+
PLL_LOCKTIME_PLL_ETH, PLL_CON3_PLL_ETH, NULL),
1783+
};
1784+
1785+
/* List of parent clocks for Muxes in CMU_HSI2 */
1786+
PNAME(mout_clkcmu_hsi2_noc_ufs_user_p) = { "oscclk", "dout_clkcmu_hsi2_noc_ufs" };
1787+
PNAME(mout_clkcmu_hsi2_ufs_embd_user_p) = { "oscclk", "dout_clkcmu_hsi2_ufs_embd" };
1788+
PNAME(mout_hsi2_ethernet_p) = { "fout_pll_eth", "mout_clkcmu_hsi2_ethernet_user" };
1789+
PNAME(mout_clkcmu_hsi2_ethernet_user_p) = { "oscclk", "dout_clkcmu_hsi2_ethernet" };
1790+
1791+
static const struct samsung_mux_clock hsi2_mux_clks[] __initconst = {
1792+
MUX(CLK_MOUT_HSI2_NOC_UFS_USER, "mout_clkcmu_hsi2_noc_ufs_user",
1793+
mout_clkcmu_hsi2_noc_ufs_user_p, PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER, 4, 1),
1794+
MUX(CLK_MOUT_HSI2_UFS_EMBD_USER, "mout_clkcmu_hsi2_ufs_embd_user",
1795+
mout_clkcmu_hsi2_ufs_embd_user_p, PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER, 4, 1),
1796+
MUX(CLK_MOUT_HSI2_ETHERNET, "mout_hsi2_ethernet",
1797+
mout_hsi2_ethernet_p, CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET, 0, 1),
1798+
MUX(CLK_MOUT_HSI2_ETHERNET_USER, "mout_clkcmu_hsi2_ethernet_user",
1799+
mout_clkcmu_hsi2_ethernet_user_p, PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER, 4, 1),
1800+
};
1801+
1802+
static const struct samsung_div_clock hsi2_div_clks[] __initconst = {
1803+
DIV(CLK_DOUT_HSI2_ETHERNET, "dout_hsi2_ethernet",
1804+
"mout_hsi2_ethernet", CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET,
1805+
0, 4),
1806+
DIV(CLK_DOUT_HSI2_ETHERNET_PTP, "dout_hsi2_ethernet_ptp",
1807+
"mout_hsi2_ethernet", CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP,
1808+
0, 4),
1809+
};
1810+
1811+
static const struct samsung_cmu_info hsi2_cmu_info __initconst = {
1812+
.pll_clks = hsi2_pll_clks,
1813+
.nr_pll_clks = ARRAY_SIZE(hsi2_pll_clks),
1814+
.mux_clks = hsi2_mux_clks,
1815+
.nr_mux_clks = ARRAY_SIZE(hsi2_mux_clks),
1816+
.div_clks = hsi2_div_clks,
1817+
.nr_div_clks = ARRAY_SIZE(hsi2_div_clks),
1818+
.nr_clk_ids = CLKS_NR_HSI2,
1819+
.clk_regs = hsi2_clk_regs,
1820+
.nr_clk_regs = ARRAY_SIZE(hsi2_clk_regs),
1821+
.clk_name = "noc",
1822+
};
1823+
17551824
static int __init exynosautov920_cmu_probe(struct platform_device *pdev)
17561825
{
17571826
const struct samsung_cmu_info *info;
@@ -1779,6 +1848,9 @@ static const struct of_device_id exynosautov920_cmu_of_match[] = {
17791848
}, {
17801849
.compatible = "samsung,exynosautov920-cmu-hsi1",
17811850
.data = &hsi1_cmu_info,
1851+
}, {
1852+
.compatible = "samsung,exynosautov920-cmu-hsi2",
1853+
.data = &hsi2_cmu_info,
17821854
},
17831855
{ }
17841856
};

‎drivers/clk/samsung/clk-gs101.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1154,7 +1154,7 @@ static const struct samsung_div_clock cmu_top_div_clks[] __initconst = {
11541154
CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
11551155
DIV(CLK_DOUT_CMU_G3AA_G3AA, "dout_cmu_g3aa_g3aa", "gout_cmu_g3aa_g3aa",
11561156
CLK_CON_DIV_CLKCMU_G3AA_G3AA, 0, 4),
1157-
DIV(CLK_DOUT_CMU_G3D_SWITCH, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd",
1157+
DIV(CLK_DOUT_CMU_G3D_BUSD, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd",
11581158
CLK_CON_DIV_CLKCMU_G3D_BUSD, 0, 4),
11591159
DIV(CLK_DOUT_CMU_G3D_GLB, "dout_cmu_g3d_glb", "gout_cmu_g3d_glb",
11601160
CLK_CON_DIV_CLKCMU_G3D_GLB, 0, 4),
@@ -2129,7 +2129,7 @@ PNAME(mout_hsi0_usbdpdbg_user_p) = { "oscclk",
21292129
"dout_cmu_hsi0_usbdpdbg" };
21302130
PNAME(mout_hsi0_bus_p) = { "mout_hsi0_bus_user",
21312131
"mout_hsi0_alt_user" };
2132-
PNAME(mout_hsi0_usb20_ref_p) = { "fout_usb_pll",
2132+
PNAME(mout_hsi0_usb20_ref_p) = { "mout_pll_usb",
21332133
"mout_hsi0_tcxo_user" };
21342134
PNAME(mout_hsi0_usb31drd_p) = { "fout_usb_pll",
21352135
"mout_hsi0_usb31drd_user",

‎include/dt-bindings/clock/samsung,exynosautov920.h‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -286,4 +286,13 @@
286286
#define CLK_MOUT_HSI1_USBDRD_USER 3
287287
#define CLK_MOUT_HSI1_USBDRD 4
288288

289+
/* CMU_HSI2 */
290+
#define FOUT_PLL_ETH 1
291+
#define CLK_MOUT_HSI2_NOC_UFS_USER 2
292+
#define CLK_MOUT_HSI2_UFS_EMBD_USER 3
293+
#define CLK_MOUT_HSI2_ETHERNET 4
294+
#define CLK_MOUT_HSI2_ETHERNET_USER 5
295+
#define CLK_DOUT_HSI2_ETHERNET 6
296+
#define CLK_DOUT_HSI2_ETHERNET_PTP 7
297+
289298
#endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */

0 commit comments

Comments
 (0)