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AngeloGioacchino Del RegnoChun-Kuang Hu
AngeloGioacchino Del Regno
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Chun-Kuang Hu
committed
dt-bindings: display: mediatek: Add OF graph support for board path
The display IPs in MediaTek SoCs support being interconnected with different instances of DDP IPs (for example, merge0 or merge1) and/or with different DDP IPs (for example, rdma can be connected with either color, dpi, dsi, merge, etc), forming a full Display Data Path that ends with an actual display. The final display pipeline is effectively board specific, as it does depend on the display that is attached to it, and eventually on the sensors supported by the board (for example, Adaptive Ambient Light would need an Ambient Light Sensor, otherwise it's pointless!), other than the output type. Add support for OF graphs to most of the MediaTek DDP (display) bindings to add flexibility to build custom hardware paths, hence enabling board specific configuration of the display pipeline and allowing to finally migrate away from using hardcoded paths. Please note that - while this commit retains retro-compatibility with old device trees - it will break the ABI for mediatek,dsi and for mediatek,dpi for the sake of consistency between the `ports` in all MediaTek DRM drivers versus DRM bridge drivers as in the previous binding, MediaTek was using `port` (implicitly, port@0) as an OUTPUT, while now the first port is an INPUT, and the second one is an OUTPUT, which is consistent with other DRM drivers which can be chained to drm/mediatek. As for maintainability concerns, I am aware that the old device tree will not be actively tested anymore, but retrocompatibility breakages will *not* be more likely to happen in the future because any addition to the graph (new drivers) will be done only for features present on newer SoCs, keeping the old ones (and their default pipeline) untouched. Reviewed-by: Rob Herring (Arm) <[email protected]> Reviewed-by: Alexandre Mergnat <[email protected]> Tested-by: Alexandre Mergnat <[email protected]> Reviewed-by: CK Hu <[email protected]> Tested-by: Michael Walle <[email protected]> # on kontron-sbc-i1200 Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Link: https://patchwork.kernel.org/project/dri-devel/patch/[email protected]/ Signed-off-by: Chun-Kuang Hu <[email protected]>
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‎Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml

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$ref: /schemas/types.yaml#/definitions/phandle-array
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maxItems: 1
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description:
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Input and output ports can have multiple endpoints, each of those
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connects to either the primary, secondary, etc, display pipeline.
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: AAL input port
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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AAL output to the next component's input, for example could be one
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of many gamma, overdrive or other blocks.
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required:
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- port@0
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- port@1
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required:
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- compatible
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- reg
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_AAL>;
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mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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aal0_in: endpoint {
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remote-endpoint = <&ccorr0_out>;
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};
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};
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port@1 {
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reg = <1>;
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aal0_out: endpoint {
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remote-endpoint = <&gamma0_in>;
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};
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};
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};
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};
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};

‎Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml

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$ref: /schemas/types.yaml#/definitions/phandle-array
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maxItems: 1
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description:
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Input and output ports can have multiple endpoints, each of those
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connects to either the primary, secondary, etc, display pipeline.
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: CCORR input port
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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CCORR output to the input of the next desired component in the
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display pipeline, usually only one of the available AAL blocks.
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required:
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- port@0
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- port@1
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required:
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- compatible
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‎Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml

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$ref: /schemas/types.yaml#/definitions/phandle-array
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maxItems: 1
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description:
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Input and output ports can have multiple endpoints, each of those
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connects to either the primary, secondary, etc, display pipeline.
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: COLOR input port
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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COLOR output to the input of the next desired component in the
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display pipeline, for example one of the available CCORR or AAL
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blocks.
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required:
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- port@0
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- port@1
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required:
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- compatible
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‎Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml

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$ref: /schemas/types.yaml#/definitions/phandle-array
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maxItems: 1
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description:
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Input and output ports can have multiple endpoints, each of those
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connects to either the primary, secondary, etc, display pipeline.
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: DITHER input, usually from a POSTMASK or GAMMA block.
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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DITHER output to the input of the next desired component in the
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display pipeline, for example one of the available DSC compressors,
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DP_INTF, DSI, LVDS or others.
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required:
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- port@0
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- port@1
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required:
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- compatible
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- reg

‎Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml

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Output port node. This port should be connected to the input port of an
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attached HDMI, LVDS or DisplayPort encoder chip.
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: DPI input port
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description: DPI output to an HDMI, LVDS or DisplayPort encoder input
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required:
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- port@0
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- port@1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- port
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oneOf:
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- required:
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- port
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- required:
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- ports
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allOf:
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- if:
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt8173-clk.h>
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dpi0: dpi@1401d000 {
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dpi: dpi@1401d000 {
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compatible = "mediatek,mt8173-dpi";
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reg = <0x1401d000 0x1000>;
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interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;

‎Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml

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$ref: /schemas/types.yaml#/definitions/phandle-array
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maxItems: 1
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description:
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Input and output ports can have multiple endpoints, each of those
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connects to either the primary, secondary, etc, display pipeline.
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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Display Stream Compression input, usually from one of the DITHER
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or MERGE blocks.
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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Display Stream Compression output to the input of the next desired
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component in the display pipeline, for example to MERGE, DP_INTF,
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DPI or DSI.
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required:
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- port@0
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- port@1
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required:
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- compatible
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‎Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml

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Output port node. This port should be connected to the input
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port of an attached DSI panel or DSI-to-eDP encoder chip.
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description:
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Input ports can have multiple endpoints, each of those connects
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to either the primary, secondary, etc, display pipeline.
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: DSI input port, usually from DITHER, DSC or MERGE
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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DSI output to an attached DSI panel, or a DSI-to-X encoder chip
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required:
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- port@0
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- port@1
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required:
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- compatible
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- clock-names
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- phys
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- phy-names
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- port
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oneOf:
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- required:
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- port
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- required:
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- ports
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unevaluatedProperties: false
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‎Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml

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include/dt-bindings/gce/<chip>-gce.h, mapping to the register of display
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function block.
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description:
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Input and output ports can have multiple endpoints, each of those
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connects to either the primary, secondary, etc, display pipeline.
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: ETHDR input, usually from one of the MERGE blocks.
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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ETHDR output to the input of the next desired component in the
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display pipeline, for example one of the available MERGE blocks,
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or others.
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required:
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- port@0
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- port@1
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required:
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- compatible
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‎Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml

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$ref: /schemas/types.yaml#/definitions/phandle-array
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maxItems: 1
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: GAMMA input, usually from one of the AAL blocks.
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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GAMMA output to the input of the next desired component in the
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display pipeline, for example one of the available DITHER or
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POSTMASK blocks.
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required:
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- port@0
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- port@1
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required:
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- compatible
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‎Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml

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$ref: /schemas/types.yaml#/definitions/phandle-array
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description:
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Input and output ports can have multiple endpoints, each of those
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connects to either the primary, secondary, etc, display pipeline.
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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MERGE input port, usually from DITHER, DPI, DSC, DSI, MDP_RDMA,
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ETHDR or even from a different MERGE block
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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MERGE output to a DSC, DPI, DP_INTF, DSI, ETHDR, Write DMA, or
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a different MERGE block, or others.
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required:
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- port@0
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- port@1
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resets:
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description: reset controller
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See Documentation/devicetree/bindings/reset/reset.txt for details.

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