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Merge branch 'dsa-en7581' into main
Lorenzo Bianconi says: ==================== Add second QDMA support for EN7581 eth controller EN7581 SoC supports two independent QDMA controllers to connect the Ethernet Frame Engine (FE) to the CPU. Introduce support for the second QDMA controller. This is a preliminary series to support multiple FE ports (e.g. connected to a second PHY controller). Changes since v1: - squash patch 6/9 and 7/9 - move some duplicated code from patch 2/9 in 1/9 - cosmetics ==================== Signed-off-by: David S. Miller <[email protected]>
2 parents 83044bf + 2b0229f commit 3608d6a

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-12
lines changed

4 files changed

+66
-12
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Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -92,6 +92,10 @@ properties:
9292
Built-in switch of the MT7988 SoC
9393
const: mediatek,mt7988-switch
9494

95+
- description:
96+
Built-in switch of the Airoha EN7581 SoC
97+
const: airoha,en7581-switch
98+
9599
reg:
96100
maxItems: 1
97101

@@ -284,7 +288,9 @@ allOf:
284288
- if:
285289
properties:
286290
compatible:
287-
const: mediatek,mt7988-switch
291+
enum:
292+
- mediatek,mt7988-switch
293+
- airoha,en7581-switch
288294
then:
289295
$ref: "#/$defs/mt7530-dsa-port"
290296
properties:

drivers/net/dsa/mt7530-mmio.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@
1111
#include "mt7530.h"
1212

1313
static const struct of_device_id mt7988_of_match[] = {
14+
{ .compatible = "airoha,en7581-switch", .data = &mt753x_table[ID_EN7581], },
1415
{ .compatible = "mediatek,mt7988-switch", .data = &mt753x_table[ID_MT7988], },
1516
{ /* sentinel */ },
1617
};

drivers/net/dsa/mt7530.c

Lines changed: 43 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1152,7 +1152,8 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
11521152
* the MT7988 SoC. Trapped frames will be forwarded to the CPU port that
11531153
* is affine to the inbound user port.
11541154
*/
1155-
if (priv->id == ID_MT7531 || priv->id == ID_MT7988)
1155+
if (priv->id == ID_MT7531 || priv->id == ID_MT7988 ||
1156+
priv->id == ID_EN7581)
11561157
mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port)));
11571158

11581159
/* CPU port gets connected to all user ports of
@@ -2207,7 +2208,7 @@ mt7530_setup_irq(struct mt7530_priv *priv)
22072208
return priv->irq ? : -EINVAL;
22082209
}
22092210

2210-
if (priv->id == ID_MT7988)
2211+
if (priv->id == ID_MT7988 || priv->id == ID_EN7581)
22112212
priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS,
22122213
&mt7988_irq_domain_ops,
22132214
priv);
@@ -2438,8 +2439,10 @@ mt7530_setup(struct dsa_switch *ds)
24382439
/* Clear link settings and enable force mode to force link down
24392440
* on all ports until they're enabled later.
24402441
*/
2441-
mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
2442-
MT7530_FORCE_MODE, MT7530_FORCE_MODE);
2442+
mt7530_rmw(priv, MT753X_PMCR_P(i),
2443+
PMCR_LINK_SETTINGS_MASK |
2444+
MT753X_FORCE_MODE(priv->id),
2445+
MT753X_FORCE_MODE(priv->id));
24432446

24442447
/* Disable forwarding by default on all ports */
24452448
mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
@@ -2550,8 +2553,10 @@ mt7531_setup_common(struct dsa_switch *ds)
25502553
/* Clear link settings and enable force mode to force link down
25512554
* on all ports until they're enabled later.
25522555
*/
2553-
mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
2554-
MT7531_FORCE_MODE_MASK, MT7531_FORCE_MODE_MASK);
2556+
mt7530_rmw(priv, MT753X_PMCR_P(i),
2557+
PMCR_LINK_SETTINGS_MASK |
2558+
MT753X_FORCE_MODE(priv->id),
2559+
MT753X_FORCE_MODE(priv->id));
25552560

25562561
/* Disable forwarding by default on all ports */
25572562
mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
@@ -2783,6 +2788,28 @@ static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port,
27832788
}
27842789
}
27852790

2791+
static void en7581_mac_port_get_caps(struct dsa_switch *ds, int port,
2792+
struct phylink_config *config)
2793+
{
2794+
switch (port) {
2795+
/* Ports which are connected to switch PHYs. There is no MII pinout. */
2796+
case 0 ... 4:
2797+
__set_bit(PHY_INTERFACE_MODE_INTERNAL,
2798+
config->supported_interfaces);
2799+
2800+
config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD;
2801+
break;
2802+
2803+
/* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */
2804+
case 6:
2805+
__set_bit(PHY_INTERFACE_MODE_INTERNAL,
2806+
config->supported_interfaces);
2807+
2808+
config->mac_capabilities |= MAC_10000FD;
2809+
break;
2810+
}
2811+
}
2812+
27862813
static void
27872814
mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
27882815
phy_interface_t interface)
@@ -3220,6 +3247,16 @@ const struct mt753x_info mt753x_table[] = {
32203247
.phy_write_c45 = mt7531_ind_c45_phy_write,
32213248
.mac_port_get_caps = mt7988_mac_port_get_caps,
32223249
},
3250+
[ID_EN7581] = {
3251+
.id = ID_EN7581,
3252+
.pcs_ops = &mt7530_pcs_ops,
3253+
.sw_setup = mt7988_setup,
3254+
.phy_read_c22 = mt7531_ind_c22_phy_read,
3255+
.phy_write_c22 = mt7531_ind_c22_phy_write,
3256+
.phy_read_c45 = mt7531_ind_c45_phy_read,
3257+
.phy_write_c45 = mt7531_ind_c45_phy_write,
3258+
.mac_port_get_caps = en7581_mac_port_get_caps,
3259+
},
32233260
};
32243261
EXPORT_SYMBOL_GPL(mt753x_table);
32253262

drivers/net/dsa/mt7530.h

Lines changed: 15 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@ enum mt753x_id {
1919
ID_MT7621 = 1,
2020
ID_MT7531 = 2,
2121
ID_MT7988 = 3,
22+
ID_EN7581 = 4,
2223
};
2324

2425
#define NUM_TRGMII_CTRL 5
@@ -64,25 +65,30 @@ enum mt753x_id {
6465
#define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x)
6566

6667
#define MT753X_MIRROR_REG(id) ((id == ID_MT7531 || \
67-
id == ID_MT7988) ? \
68+
id == ID_MT7988 || \
69+
id == ID_EN7581) ? \
6870
MT7531_CFC : MT753X_MFC)
6971

7072
#define MT753X_MIRROR_EN(id) ((id == ID_MT7531 || \
71-
id == ID_MT7988) ? \
73+
id == ID_MT7988 || \
74+
id == ID_EN7581) ? \
7275
MT7531_MIRROR_EN : MT7530_MIRROR_EN)
7376

7477
#define MT753X_MIRROR_PORT_MASK(id) ((id == ID_MT7531 || \
75-
id == ID_MT7988) ? \
78+
id == ID_MT7988 || \
79+
id == ID_EN7581) ? \
7680
MT7531_MIRROR_PORT_MASK : \
7781
MT7530_MIRROR_PORT_MASK)
7882

7983
#define MT753X_MIRROR_PORT_GET(id, val) ((id == ID_MT7531 || \
80-
id == ID_MT7988) ? \
84+
id == ID_MT7988 || \
85+
id == ID_EN7581) ? \
8186
MT7531_MIRROR_PORT_GET(val) : \
8287
MT7530_MIRROR_PORT_GET(val))
8388

8489
#define MT753X_MIRROR_PORT_SET(id, val) ((id == ID_MT7531 || \
85-
id == ID_MT7988) ? \
90+
id == ID_MT7988 || \
91+
id == ID_EN7581) ? \
8692
MT7531_MIRROR_PORT_SET(val) : \
8793
MT7530_MIRROR_PORT_SET(val))
8894

@@ -355,6 +361,10 @@ enum mt7530_vlan_port_acc_frm {
355361
MT7531_FORCE_MODE_TX_FC | \
356362
MT7531_FORCE_MODE_EEE100 | \
357363
MT7531_FORCE_MODE_EEE1G)
364+
#define MT753X_FORCE_MODE(id) ((id == ID_MT7531 || \
365+
id == ID_MT7988) ? \
366+
MT7531_FORCE_MODE_MASK : \
367+
MT7530_FORCE_MODE)
358368
#define PMCR_LINK_SETTINGS_MASK (PMCR_MAC_TX_EN | PMCR_MAC_RX_EN | \
359369
PMCR_FORCE_EEE1G | \
360370
PMCR_FORCE_EEE100 | \

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