@@ -1152,7 +1152,8 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
11521152 * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that
11531153 * is affine to the inbound user port.
11541154 */
1155- if (priv -> id == ID_MT7531 || priv -> id == ID_MT7988 )
1155+ if (priv -> id == ID_MT7531 || priv -> id == ID_MT7988 ||
1156+ priv -> id == ID_EN7581 )
11561157 mt7530_set (priv , MT7531_CFC , MT7531_CPU_PMAP (BIT (port )));
11571158
11581159 /* CPU port gets connected to all user ports of
@@ -2207,7 +2208,7 @@ mt7530_setup_irq(struct mt7530_priv *priv)
22072208 return priv -> irq ? : - EINVAL ;
22082209 }
22092210
2210- if (priv -> id == ID_MT7988 )
2211+ if (priv -> id == ID_MT7988 || priv -> id == ID_EN7581 )
22112212 priv -> irq_domain = irq_domain_add_linear (np , MT7530_NUM_PHYS ,
22122213 & mt7988_irq_domain_ops ,
22132214 priv );
@@ -2438,8 +2439,10 @@ mt7530_setup(struct dsa_switch *ds)
24382439 /* Clear link settings and enable force mode to force link down
24392440 * on all ports until they're enabled later.
24402441 */
2441- mt7530_rmw (priv , MT753X_PMCR_P (i ), PMCR_LINK_SETTINGS_MASK |
2442- MT7530_FORCE_MODE , MT7530_FORCE_MODE );
2442+ mt7530_rmw (priv , MT753X_PMCR_P (i ),
2443+ PMCR_LINK_SETTINGS_MASK |
2444+ MT753X_FORCE_MODE (priv -> id ),
2445+ MT753X_FORCE_MODE (priv -> id ));
24432446
24442447 /* Disable forwarding by default on all ports */
24452448 mt7530_rmw (priv , MT7530_PCR_P (i ), PCR_MATRIX_MASK ,
@@ -2550,8 +2553,10 @@ mt7531_setup_common(struct dsa_switch *ds)
25502553 /* Clear link settings and enable force mode to force link down
25512554 * on all ports until they're enabled later.
25522555 */
2553- mt7530_rmw (priv , MT753X_PMCR_P (i ), PMCR_LINK_SETTINGS_MASK |
2554- MT7531_FORCE_MODE_MASK , MT7531_FORCE_MODE_MASK );
2556+ mt7530_rmw (priv , MT753X_PMCR_P (i ),
2557+ PMCR_LINK_SETTINGS_MASK |
2558+ MT753X_FORCE_MODE (priv -> id ),
2559+ MT753X_FORCE_MODE (priv -> id ));
25552560
25562561 /* Disable forwarding by default on all ports */
25572562 mt7530_rmw (priv , MT7530_PCR_P (i ), PCR_MATRIX_MASK ,
@@ -2783,6 +2788,28 @@ static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port,
27832788 }
27842789}
27852790
2791+ static void en7581_mac_port_get_caps (struct dsa_switch * ds , int port ,
2792+ struct phylink_config * config )
2793+ {
2794+ switch (port ) {
2795+ /* Ports which are connected to switch PHYs. There is no MII pinout. */
2796+ case 0 ... 4 :
2797+ __set_bit (PHY_INTERFACE_MODE_INTERNAL ,
2798+ config -> supported_interfaces );
2799+
2800+ config -> mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD ;
2801+ break ;
2802+
2803+ /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */
2804+ case 6 :
2805+ __set_bit (PHY_INTERFACE_MODE_INTERNAL ,
2806+ config -> supported_interfaces );
2807+
2808+ config -> mac_capabilities |= MAC_10000FD ;
2809+ break ;
2810+ }
2811+ }
2812+
27862813static void
27872814mt7530_mac_config (struct dsa_switch * ds , int port , unsigned int mode ,
27882815 phy_interface_t interface )
@@ -3220,6 +3247,16 @@ const struct mt753x_info mt753x_table[] = {
32203247 .phy_write_c45 = mt7531_ind_c45_phy_write ,
32213248 .mac_port_get_caps = mt7988_mac_port_get_caps ,
32223249 },
3250+ [ID_EN7581 ] = {
3251+ .id = ID_EN7581 ,
3252+ .pcs_ops = & mt7530_pcs_ops ,
3253+ .sw_setup = mt7988_setup ,
3254+ .phy_read_c22 = mt7531_ind_c22_phy_read ,
3255+ .phy_write_c22 = mt7531_ind_c22_phy_write ,
3256+ .phy_read_c45 = mt7531_ind_c45_phy_read ,
3257+ .phy_write_c45 = mt7531_ind_c45_phy_write ,
3258+ .mac_port_get_caps = en7581_mac_port_get_caps ,
3259+ },
32233260};
32243261EXPORT_SYMBOL_GPL (mt753x_table );
32253262
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