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masneybbroonie
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ASoC: codecs: rt5682: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Mark Brown <[email protected]>
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sound/soc/codecs/rt5682.c

Lines changed: 14 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -2675,8 +2675,8 @@ static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw,
26752675
return rt5682->lrck[RT5682_AIF1];
26762676
}
26772677

2678-
static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
2679-
unsigned long *parent_rate)
2678+
static int rt5682_wclk_determine_rate(struct clk_hw *hw,
2679+
struct clk_rate_request *req)
26802680
{
26812681
struct rt5682_priv *rt5682 =
26822682
container_of(hw, struct rt5682_priv,
@@ -2689,13 +2689,13 @@ static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
26892689
* Only accept to set wclk rate to 44.1k or 48kHz.
26902690
* It will force to 48kHz if not both.
26912691
*/
2692-
if (rate != CLK_48 && rate != CLK_44) {
2692+
if (req->rate != CLK_48 && req->rate != CLK_44) {
26932693
dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n",
26942694
__func__, clk_name, CLK_44, CLK_48);
2695-
rate = CLK_48;
2695+
req->rate = CLK_48;
26962696
}
26972697

2698-
return rate;
2698+
return 0;
26992699
}
27002700

27012701
static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -2795,15 +2795,15 @@ static unsigned long rt5682_bclk_get_factor(unsigned long rate,
27952795
return 256;
27962796
}
27972797

2798-
static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
2799-
unsigned long *parent_rate)
2798+
static int rt5682_bclk_determine_rate(struct clk_hw *hw,
2799+
struct clk_rate_request *req)
28002800
{
28012801
struct rt5682_priv *rt5682 =
28022802
container_of(hw, struct rt5682_priv,
28032803
dai_clks_hw[RT5682_DAI_BCLK_IDX]);
28042804
unsigned long factor;
28052805

2806-
if (!*parent_rate || !rt5682_clk_check(rt5682))
2806+
if (!req->best_parent_rate || !rt5682_clk_check(rt5682))
28072807
return -EINVAL;
28082808

28092809
/*
@@ -2813,9 +2813,11 @@ static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
28132813
* and find the appropriate multiplier of BCLK to
28142814
* get the rounded down BCLK value.
28152815
*/
2816-
factor = rt5682_bclk_get_factor(rate, *parent_rate);
2816+
factor = rt5682_bclk_get_factor(req->rate, req->best_parent_rate);
2817+
2818+
req->rate = req->best_parent_rate * factor;
28172819

2818-
return *parent_rate * factor;
2820+
return 0;
28192821
}
28202822

28212823
static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -2849,12 +2851,12 @@ static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = {
28492851
.prepare = rt5682_wclk_prepare,
28502852
.unprepare = rt5682_wclk_unprepare,
28512853
.recalc_rate = rt5682_wclk_recalc_rate,
2852-
.round_rate = rt5682_wclk_round_rate,
2854+
.determine_rate = rt5682_wclk_determine_rate,
28532855
.set_rate = rt5682_wclk_set_rate,
28542856
},
28552857
[RT5682_DAI_BCLK_IDX] = {
28562858
.recalc_rate = rt5682_bclk_recalc_rate,
2857-
.round_rate = rt5682_bclk_round_rate,
2859+
.determine_rate = rt5682_bclk_determine_rate,
28582860
.set_rate = rt5682_bclk_set_rate,
28592861
},
28602862
};

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