drm/amd/pm/powerplay/smumgr: Fix PCIeBootLinkLevel value on Iceland

Previously this was initialized with zero which represented PCIe Gen
1.0 instead of using the
maximum value from the speed table which is the behaviour of all other
smumgr implementations.

Fixes: 18aafc5 ("drm/amd/powerplay: implement fw related smu interface for iceland.")
Signed-off-by: John Smith <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
(cherry picked from commit 92b0a6ae6672857ddeabf892223943d2f0e06c97)

Author: irql-notlessorequal

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

@@ -2028,7 +2028,7 @@ static int iceland_init_smc_table(struct pp_hwmgr *hwmgr)
 	table->VoltageResponseTime  = 0;
 	table->PhaseResponseTime  = 0;
 	table->MemoryThermThrottleEnable  = 1;
-	table->PCIeBootLinkLevel = 0;
+	table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count);
 	table->PCIeGenInterval = 1;
 
 	result = iceland_populate_smc_svi2_config(hwmgr, table);