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| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/i3c/renesas,i3c.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: Renesas RZ/G3S and RZ/G3E I3C Bus Interface |
| 8 | + |
| 9 | +maintainers: |
| 10 | + - Wolfram Sang <[email protected]> |
| 11 | + - Tommaso Merciai <[email protected]> |
| 12 | + |
| 13 | +properties: |
| 14 | + compatible: |
| 15 | + items: |
| 16 | + - enum: |
| 17 | + - renesas,r9a08g045-i3c # RZ/G3S |
| 18 | + - renesas,r9a09g047-i3c # RZ/G3E |
| 19 | + |
| 20 | + reg: |
| 21 | + maxItems: 1 |
| 22 | + |
| 23 | + interrupts: |
| 24 | + items: |
| 25 | + - description: Non-recoverable internal error interrupt |
| 26 | + - description: Normal transfer error interrupt |
| 27 | + - description: Normal transfer abort interrupt |
| 28 | + - description: Normal response status buffer full interrupt |
| 29 | + - description: Normal command buffer empty interrupt |
| 30 | + - description: Normal IBI status buffer full interrupt |
| 31 | + - description: Normal Rx data buffer full interrupt |
| 32 | + - description: Normal Tx data buffer empty interrupt |
| 33 | + - description: Normal receive status buffer full interrupt |
| 34 | + - description: START condition detection interrupt |
| 35 | + - description: STOP condition detection interrupt |
| 36 | + - description: Transmit end interrupt |
| 37 | + - description: NACK detection interrupt |
| 38 | + - description: Arbitration lost interrupt |
| 39 | + - description: Timeout detection interrupt |
| 40 | + - description: Wake-up condition detection interrupt |
| 41 | + - description: HDR Exit Pattern detection interrupt |
| 42 | + minItems: 16 |
| 43 | + |
| 44 | + interrupt-names: |
| 45 | + items: |
| 46 | + - const: ierr |
| 47 | + - const: terr |
| 48 | + - const: abort |
| 49 | + - const: resp |
| 50 | + - const: cmd |
| 51 | + - const: ibi |
| 52 | + - const: rx |
| 53 | + - const: tx |
| 54 | + - const: rcv |
| 55 | + - const: st |
| 56 | + - const: sp |
| 57 | + - const: tend |
| 58 | + - const: nack |
| 59 | + - const: al |
| 60 | + - const: tmo |
| 61 | + - const: wu |
| 62 | + - const: exit |
| 63 | + minItems: 16 |
| 64 | + |
| 65 | + clocks: |
| 66 | + items: |
| 67 | + - description: APB bus clock |
| 68 | + - description: transfer clock |
| 69 | + - description: SFRs clock |
| 70 | + minItems: 2 |
| 71 | + |
| 72 | + clock-names: |
| 73 | + items: |
| 74 | + - const: pclk |
| 75 | + - const: tclk |
| 76 | + - const: pclkrw |
| 77 | + minItems: 2 |
| 78 | + |
| 79 | + power-domains: |
| 80 | + maxItems: 1 |
| 81 | + |
| 82 | + resets: |
| 83 | + items: |
| 84 | + - description: Reset signal |
| 85 | + - description: APB interface reset signal/SCAN reset signal |
| 86 | + |
| 87 | + reset-names: |
| 88 | + items: |
| 89 | + - const: presetn |
| 90 | + - const: tresetn |
| 91 | + |
| 92 | +required: |
| 93 | + - compatible |
| 94 | + - reg |
| 95 | + - interrupts |
| 96 | + - interrupt-names |
| 97 | + - clock-names |
| 98 | + - clocks |
| 99 | + - power-domains |
| 100 | + - resets |
| 101 | + - reset-names |
| 102 | + |
| 103 | +allOf: |
| 104 | + - $ref: i3c.yaml# |
| 105 | + |
| 106 | + - if: |
| 107 | + properties: |
| 108 | + compatible: |
| 109 | + contains: |
| 110 | + const: renesas,r9a08g045-i3c |
| 111 | + then: |
| 112 | + properties: |
| 113 | + clocks: |
| 114 | + maxItems: 2 |
| 115 | + clock-names: |
| 116 | + maxItems: 2 |
| 117 | + interrupts: |
| 118 | + minItems: 17 |
| 119 | + interrupt-names: |
| 120 | + minItems: 17 |
| 121 | + |
| 122 | + - if: |
| 123 | + properties: |
| 124 | + compatible: |
| 125 | + contains: |
| 126 | + const: renesas,r9a09g047-i3c |
| 127 | + then: |
| 128 | + properties: |
| 129 | + clocks: |
| 130 | + minItems: 3 |
| 131 | + clock-names: |
| 132 | + minItems: 3 |
| 133 | + interrupts: |
| 134 | + maxItems: 16 |
| 135 | + interrupt-names: |
| 136 | + maxItems: 16 |
| 137 | + |
| 138 | +unevaluatedProperties: false |
| 139 | + |
| 140 | +examples: |
| 141 | + - | |
| 142 | + #include <dt-bindings/clock/r9a08g045-cpg.h> |
| 143 | + #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 144 | +
|
| 145 | + i3c@1005b000 { |
| 146 | + compatible = "renesas,r9a08g045-i3c"; |
| 147 | + reg = <0x1005b000 0x1000>; |
| 148 | + clocks = <&cpg CPG_MOD R9A08G045_I3C_PCLK>, |
| 149 | + <&cpg CPG_MOD R9A08G045_I3C_TCLK>; |
| 150 | + clock-names = "pclk", "tclk"; |
| 151 | + interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, |
| 152 | + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, |
| 153 | + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, |
| 154 | + <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>, |
| 155 | + <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>, |
| 156 | + <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, |
| 157 | + <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, |
| 158 | + <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, |
| 159 | + <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, |
| 160 | + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, |
| 161 | + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, |
| 162 | + <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, |
| 163 | + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, |
| 164 | + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, |
| 165 | + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, |
| 166 | + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, |
| 167 | + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; |
| 168 | + interrupt-names = "ierr", "terr", "abort", "resp", |
| 169 | + "cmd", "ibi", "rx", "tx", "rcv", |
| 170 | + "st", "sp", "tend", "nack", |
| 171 | + "al", "tmo", "wu", "exit"; |
| 172 | + resets = <&cpg R9A08G045_I3C_PRESETN>, |
| 173 | + <&cpg R9A08G045_I3C_TRESETN>; |
| 174 | + reset-names = "presetn", "tresetn"; |
| 175 | + power-domains = <&cpg>; |
| 176 | + #address-cells = <3>; |
| 177 | + #size-cells = <0>; |
| 178 | + }; |
| 179 | +... |
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