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net: ti: icssg-prueth: Add support for PA Stats
Add support for dumping PA stats registers via ethtool. Firmware maintained stats are stored at PA Stats registers. Also modify emac_get_strings() API to use ethtool_puts(). This commit also maintains consistency between miig_stats and pa_stats by - renaming the array icssg_all_stats to icssg_all_miig_stats - renaming the structure icssg_stats to icssg_miig_stats - renaming ICSSG_STATS() to ICSSG_MIIG_STATS() - changing order of stats related data structures and arrays so that data structures of a certain stats type is clubbed together. Signed-off-by: MD Danish Anwar <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
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5 files changed

+140
-83
lines changed

5 files changed

+140
-83
lines changed

‎drivers/net/ethernet/ti/icssg/icssg_ethtool.c‎

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -83,13 +83,11 @@ static void emac_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
8383

8484
switch (stringset) {
8585
case ETH_SS_STATS:
86-
for (i = 0; i < ARRAY_SIZE(icssg_all_stats); i++) {
87-
if (!icssg_all_stats[i].standard_stats) {
88-
memcpy(p, icssg_all_stats[i].name,
89-
ETH_GSTRING_LEN);
90-
p += ETH_GSTRING_LEN;
91-
}
92-
}
86+
for (i = 0; i < ARRAY_SIZE(icssg_all_miig_stats); i++)
87+
if (!icssg_all_miig_stats[i].standard_stats)
88+
ethtool_puts(&p, icssg_all_miig_stats[i].name);
89+
for (i = 0; i < ARRAY_SIZE(icssg_all_pa_stats); i++)
90+
ethtool_puts(&p, icssg_all_pa_stats[i].name);
9391
break;
9492
default:
9593
break;
@@ -104,9 +102,12 @@ static void emac_get_ethtool_stats(struct net_device *ndev,
104102

105103
emac_update_hardware_stats(emac);
106104

107-
for (i = 0; i < ARRAY_SIZE(icssg_all_stats); i++)
108-
if (!icssg_all_stats[i].standard_stats)
105+
for (i = 0; i < ARRAY_SIZE(icssg_all_miig_stats); i++)
106+
if (!icssg_all_miig_stats[i].standard_stats)
109107
*(data++) = emac->stats[i];
108+
109+
for (i = 0; i < ARRAY_SIZE(icssg_all_pa_stats); i++)
110+
*(data++) = emac->pa_stats[i];
110111
}
111112

112113
static int emac_get_ts_info(struct net_device *ndev,

‎drivers/net/ethernet/ti/icssg/icssg_prueth.c‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1182,6 +1182,12 @@ static int prueth_probe(struct platform_device *pdev)
11821182
return -ENODEV;
11831183
}
11841184

1185+
prueth->pa_stats = syscon_regmap_lookup_by_phandle(np, "ti,pa-stats");
1186+
if (IS_ERR(prueth->pa_stats)) {
1187+
dev_err(dev, "couldn't get ti,pa-stats syscon regmap\n");
1188+
return -ENODEV;
1189+
}
1190+
11851191
if (eth0_node) {
11861192
ret = prueth_get_cores(prueth, ICSS_SLICE0, false);
11871193
if (ret)

‎drivers/net/ethernet/ti/icssg/icssg_prueth.h‎

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -50,8 +50,10 @@
5050

5151
#define ICSSG_MAX_RFLOWS 8 /* per slice */
5252

53+
#define ICSSG_NUM_PA_STATS 4
54+
#define ICSSG_NUM_MIIG_STATS 60
5355
/* Number of ICSSG related stats */
54-
#define ICSSG_NUM_STATS 60
56+
#define ICSSG_NUM_STATS (ICSSG_NUM_MIIG_STATS + ICSSG_NUM_PA_STATS)
5557
#define ICSSG_NUM_STANDARD_STATS 31
5658
#define ICSSG_NUM_ETHTOOL_STATS (ICSSG_NUM_STATS - ICSSG_NUM_STANDARD_STATS)
5759

@@ -190,7 +192,8 @@ struct prueth_emac {
190192
int port_vlan;
191193

192194
struct delayed_work stats_work;
193-
u64 stats[ICSSG_NUM_STATS];
195+
u64 stats[ICSSG_NUM_MIIG_STATS];
196+
u64 pa_stats[ICSSG_NUM_PA_STATS];
194197

195198
/* RX IRQ Coalescing Related */
196199
struct hrtimer rx_hrtimer;
@@ -230,6 +233,7 @@ struct icssg_firmwares {
230233
* @registered_netdevs: list of registered netdevs
231234
* @miig_rt: regmap to mii_g_rt block
232235
* @mii_rt: regmap to mii_rt block
236+
* @pa_stats: regmap to pa_stats block
233237
* @pru_id: ID for each of the PRUs
234238
* @pdev: pointer to ICSSG platform device
235239
* @pdata: pointer to platform data for ICSSG driver
@@ -263,6 +267,7 @@ struct prueth {
263267
struct net_device *registered_netdevs[PRUETH_NUM_MACS];
264268
struct regmap *miig_rt;
265269
struct regmap *mii_rt;
270+
struct regmap *pa_stats;
266271

267272
enum pruss_pru_id pru_id[PRUSS_NUM_PRUS];
268273
struct platform_device *pdev;

‎drivers/net/ethernet/ti/icssg/icssg_stats.c‎

Lines changed: 22 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@
1111

1212
#define ICSSG_TX_PACKET_OFFSET 0xA0
1313
#define ICSSG_TX_BYTE_OFFSET 0xEC
14+
#define ICSSG_FW_STATS_BASE 0x0248
1415

1516
static u32 stats_base[] = { 0x54c, /* Slice 0 stats start */
1617
0xb18, /* Slice 1 stats start */
@@ -22,24 +23,31 @@ void emac_update_hardware_stats(struct prueth_emac *emac)
2223
int slice = prueth_emac_slice(emac);
2324
u32 base = stats_base[slice];
2425
u32 tx_pkt_cnt = 0;
25-
u32 val;
26+
u32 val, reg;
2627
int i;
2728

28-
for (i = 0; i < ARRAY_SIZE(icssg_all_stats); i++) {
29+
for (i = 0; i < ARRAY_SIZE(icssg_all_miig_stats); i++) {
2930
regmap_read(prueth->miig_rt,
30-
base + icssg_all_stats[i].offset,
31+
base + icssg_all_miig_stats[i].offset,
3132
&val);
3233
regmap_write(prueth->miig_rt,
33-
base + icssg_all_stats[i].offset,
34+
base + icssg_all_miig_stats[i].offset,
3435
val);
3536

36-
if (icssg_all_stats[i].offset == ICSSG_TX_PACKET_OFFSET)
37+
if (icssg_all_miig_stats[i].offset == ICSSG_TX_PACKET_OFFSET)
3738
tx_pkt_cnt = val;
3839

3940
emac->stats[i] += val;
40-
if (icssg_all_stats[i].offset == ICSSG_TX_BYTE_OFFSET)
41+
if (icssg_all_miig_stats[i].offset == ICSSG_TX_BYTE_OFFSET)
4142
emac->stats[i] -= tx_pkt_cnt * 8;
4243
}
44+
45+
for (i = 0; i < ARRAY_SIZE(icssg_all_pa_stats); i++) {
46+
reg = ICSSG_FW_STATS_BASE + icssg_all_pa_stats[i].offset *
47+
PRUETH_NUM_MACS + slice * sizeof(u32);
48+
regmap_read(prueth->pa_stats, reg, &val);
49+
emac->pa_stats[i] += val;
50+
}
4351
}
4452

4553
void icssg_stats_work_handler(struct work_struct *work)
@@ -57,9 +65,14 @@ int emac_get_stat_by_name(struct prueth_emac *emac, char *stat_name)
5765
{
5866
int i;
5967

60-
for (i = 0; i < ARRAY_SIZE(icssg_all_stats); i++) {
61-
if (!strcmp(icssg_all_stats[i].name, stat_name))
62-
return emac->stats[icssg_all_stats[i].offset / sizeof(u32)];
68+
for (i = 0; i < ARRAY_SIZE(icssg_all_miig_stats); i++) {
69+
if (!strcmp(icssg_all_miig_stats[i].name, stat_name))
70+
return emac->stats[icssg_all_miig_stats[i].offset / sizeof(u32)];
71+
}
72+
73+
for (i = 0; i < ARRAY_SIZE(icssg_all_pa_stats); i++) {
74+
if (!strcmp(icssg_all_pa_stats[i].name, stat_name))
75+
return emac->pa_stats[icssg_all_pa_stats[i].offset / sizeof(u32)];
6376
}
6477

6578
netdev_err(emac->ndev, "Invalid stats %s\n", stat_name);

‎drivers/net/ethernet/ti/icssg/icssg_stats.h‎

Lines changed: 95 additions & 63 deletions
Original file line numberDiff line numberDiff line change
@@ -77,82 +77,114 @@ struct miig_stats_regs {
7777
u32 tx_bytes;
7878
};
7979

80-
#define ICSSG_STATS(field, stats_type) \
80+
#define ICSSG_MIIG_STATS(field, stats_type) \
8181
{ \
8282
#field, \
8383
offsetof(struct miig_stats_regs, field), \
8484
stats_type \
8585
}
8686

87-
struct icssg_stats {
87+
struct icssg_miig_stats {
8888
char name[ETH_GSTRING_LEN];
8989
u32 offset;
9090
bool standard_stats;
9191
};
9292

93-
static const struct icssg_stats icssg_all_stats[] = {
93+
static const struct icssg_miig_stats icssg_all_miig_stats[] = {
9494
/* Rx */
95-
ICSSG_STATS(rx_packets, true),
96-
ICSSG_STATS(rx_broadcast_frames, false),
97-
ICSSG_STATS(rx_multicast_frames, true),
98-
ICSSG_STATS(rx_crc_errors, true),
99-
ICSSG_STATS(rx_mii_error_frames, false),
100-
ICSSG_STATS(rx_odd_nibble_frames, false),
101-
ICSSG_STATS(rx_frame_max_size, true),
102-
ICSSG_STATS(rx_max_size_error_frames, false),
103-
ICSSG_STATS(rx_frame_min_size, true),
104-
ICSSG_STATS(rx_min_size_error_frames, false),
105-
ICSSG_STATS(rx_over_errors, true),
106-
ICSSG_STATS(rx_class0_hits, false),
107-
ICSSG_STATS(rx_class1_hits, false),
108-
ICSSG_STATS(rx_class2_hits, false),
109-
ICSSG_STATS(rx_class3_hits, false),
110-
ICSSG_STATS(rx_class4_hits, false),
111-
ICSSG_STATS(rx_class5_hits, false),
112-
ICSSG_STATS(rx_class6_hits, false),
113-
ICSSG_STATS(rx_class7_hits, false),
114-
ICSSG_STATS(rx_class8_hits, false),
115-
ICSSG_STATS(rx_class9_hits, false),
116-
ICSSG_STATS(rx_class10_hits, false),
117-
ICSSG_STATS(rx_class11_hits, false),
118-
ICSSG_STATS(rx_class12_hits, false),
119-
ICSSG_STATS(rx_class13_hits, false),
120-
ICSSG_STATS(rx_class14_hits, false),
121-
ICSSG_STATS(rx_class15_hits, false),
122-
ICSSG_STATS(rx_smd_frags, false),
123-
ICSSG_STATS(rx_bucket1_size, true),
124-
ICSSG_STATS(rx_bucket2_size, true),
125-
ICSSG_STATS(rx_bucket3_size, true),
126-
ICSSG_STATS(rx_bucket4_size, true),
127-
ICSSG_STATS(rx_64B_frames, true),
128-
ICSSG_STATS(rx_bucket1_frames, true),
129-
ICSSG_STATS(rx_bucket2_frames, true),
130-
ICSSG_STATS(rx_bucket3_frames, true),
131-
ICSSG_STATS(rx_bucket4_frames, true),
132-
ICSSG_STATS(rx_bucket5_frames, true),
133-
ICSSG_STATS(rx_bytes, true),
134-
ICSSG_STATS(rx_tx_total_bytes, false),
95+
ICSSG_MIIG_STATS(rx_packets, true),
96+
ICSSG_MIIG_STATS(rx_broadcast_frames, false),
97+
ICSSG_MIIG_STATS(rx_multicast_frames, true),
98+
ICSSG_MIIG_STATS(rx_crc_errors, true),
99+
ICSSG_MIIG_STATS(rx_mii_error_frames, false),
100+
ICSSG_MIIG_STATS(rx_odd_nibble_frames, false),
101+
ICSSG_MIIG_STATS(rx_frame_max_size, true),
102+
ICSSG_MIIG_STATS(rx_max_size_error_frames, false),
103+
ICSSG_MIIG_STATS(rx_frame_min_size, true),
104+
ICSSG_MIIG_STATS(rx_min_size_error_frames, false),
105+
ICSSG_MIIG_STATS(rx_over_errors, true),
106+
ICSSG_MIIG_STATS(rx_class0_hits, false),
107+
ICSSG_MIIG_STATS(rx_class1_hits, false),
108+
ICSSG_MIIG_STATS(rx_class2_hits, false),
109+
ICSSG_MIIG_STATS(rx_class3_hits, false),
110+
ICSSG_MIIG_STATS(rx_class4_hits, false),
111+
ICSSG_MIIG_STATS(rx_class5_hits, false),
112+
ICSSG_MIIG_STATS(rx_class6_hits, false),
113+
ICSSG_MIIG_STATS(rx_class7_hits, false),
114+
ICSSG_MIIG_STATS(rx_class8_hits, false),
115+
ICSSG_MIIG_STATS(rx_class9_hits, false),
116+
ICSSG_MIIG_STATS(rx_class10_hits, false),
117+
ICSSG_MIIG_STATS(rx_class11_hits, false),
118+
ICSSG_MIIG_STATS(rx_class12_hits, false),
119+
ICSSG_MIIG_STATS(rx_class13_hits, false),
120+
ICSSG_MIIG_STATS(rx_class14_hits, false),
121+
ICSSG_MIIG_STATS(rx_class15_hits, false),
122+
ICSSG_MIIG_STATS(rx_smd_frags, false),
123+
ICSSG_MIIG_STATS(rx_bucket1_size, true),
124+
ICSSG_MIIG_STATS(rx_bucket2_size, true),
125+
ICSSG_MIIG_STATS(rx_bucket3_size, true),
126+
ICSSG_MIIG_STATS(rx_bucket4_size, true),
127+
ICSSG_MIIG_STATS(rx_64B_frames, true),
128+
ICSSG_MIIG_STATS(rx_bucket1_frames, true),
129+
ICSSG_MIIG_STATS(rx_bucket2_frames, true),
130+
ICSSG_MIIG_STATS(rx_bucket3_frames, true),
131+
ICSSG_MIIG_STATS(rx_bucket4_frames, true),
132+
ICSSG_MIIG_STATS(rx_bucket5_frames, true),
133+
ICSSG_MIIG_STATS(rx_bytes, true),
134+
ICSSG_MIIG_STATS(rx_tx_total_bytes, false),
135135
/* Tx */
136-
ICSSG_STATS(tx_packets, true),
137-
ICSSG_STATS(tx_broadcast_frames, false),
138-
ICSSG_STATS(tx_multicast_frames, false),
139-
ICSSG_STATS(tx_odd_nibble_frames, false),
140-
ICSSG_STATS(tx_underflow_errors, false),
141-
ICSSG_STATS(tx_frame_max_size, true),
142-
ICSSG_STATS(tx_max_size_error_frames, false),
143-
ICSSG_STATS(tx_frame_min_size, true),
144-
ICSSG_STATS(tx_min_size_error_frames, false),
145-
ICSSG_STATS(tx_bucket1_size, true),
146-
ICSSG_STATS(tx_bucket2_size, true),
147-
ICSSG_STATS(tx_bucket3_size, true),
148-
ICSSG_STATS(tx_bucket4_size, true),
149-
ICSSG_STATS(tx_64B_frames, true),
150-
ICSSG_STATS(tx_bucket1_frames, true),
151-
ICSSG_STATS(tx_bucket2_frames, true),
152-
ICSSG_STATS(tx_bucket3_frames, true),
153-
ICSSG_STATS(tx_bucket4_frames, true),
154-
ICSSG_STATS(tx_bucket5_frames, true),
155-
ICSSG_STATS(tx_bytes, true),
136+
ICSSG_MIIG_STATS(tx_packets, true),
137+
ICSSG_MIIG_STATS(tx_broadcast_frames, false),
138+
ICSSG_MIIG_STATS(tx_multicast_frames, false),
139+
ICSSG_MIIG_STATS(tx_odd_nibble_frames, false),
140+
ICSSG_MIIG_STATS(tx_underflow_errors, false),
141+
ICSSG_MIIG_STATS(tx_frame_max_size, true),
142+
ICSSG_MIIG_STATS(tx_max_size_error_frames, false),
143+
ICSSG_MIIG_STATS(tx_frame_min_size, true),
144+
ICSSG_MIIG_STATS(tx_min_size_error_frames, false),
145+
ICSSG_MIIG_STATS(tx_bucket1_size, true),
146+
ICSSG_MIIG_STATS(tx_bucket2_size, true),
147+
ICSSG_MIIG_STATS(tx_bucket3_size, true),
148+
ICSSG_MIIG_STATS(tx_bucket4_size, true),
149+
ICSSG_MIIG_STATS(tx_64B_frames, true),
150+
ICSSG_MIIG_STATS(tx_bucket1_frames, true),
151+
ICSSG_MIIG_STATS(tx_bucket2_frames, true),
152+
ICSSG_MIIG_STATS(tx_bucket3_frames, true),
153+
ICSSG_MIIG_STATS(tx_bucket4_frames, true),
154+
ICSSG_MIIG_STATS(tx_bucket5_frames, true),
155+
ICSSG_MIIG_STATS(tx_bytes, true),
156+
};
157+
158+
/**
159+
* struct pa_stats_regs - ICSSG Firmware maintained PA Stats register
160+
* @fw_rx_cnt: Number of valid packets sent by Rx PRU to Host on PSI
161+
* @fw_tx_cnt: Number of valid packets copied by RTU0 to Tx queues
162+
* @fw_tx_pre_overflow: Host Egress Q (Pre-emptible) Overflow Counter
163+
* @fw_tx_exp_overflow: Host Egress Q (Express) Overflow Counter
164+
*/
165+
struct pa_stats_regs {
166+
u32 fw_rx_cnt;
167+
u32 fw_tx_cnt;
168+
u32 fw_tx_pre_overflow;
169+
u32 fw_tx_exp_overflow;
170+
};
171+
172+
#define ICSSG_PA_STATS(field) \
173+
{ \
174+
#field, \
175+
offsetof(struct pa_stats_regs, field), \
176+
}
177+
178+
struct icssg_pa_stats {
179+
char name[ETH_GSTRING_LEN];
180+
u32 offset;
181+
};
182+
183+
static const struct icssg_pa_stats icssg_all_pa_stats[] = {
184+
ICSSG_PA_STATS(fw_rx_cnt),
185+
ICSSG_PA_STATS(fw_tx_cnt),
186+
ICSSG_PA_STATS(fw_tx_pre_overflow),
187+
ICSSG_PA_STATS(fw_tx_exp_overflow),
156188
};
157189

158190
#endif /* __NET_TI_ICSSG_STATS_H */

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