2020#include <linux/of.h>
2121#include <linux/of_device.h>
2222#include <linux/bitfield.h>
23+ #include <linux/hw_bitfield.h>
2324#include <linux/bits.h>
2425#include <linux/perf_event.h>
2526
3031
3132#define DMC_MAX_CHANNELS 4
3233
33- #define HIWORD_UPDATE (val , mask ) ((val) | (mask) << 16)
34-
3534/* DDRMON_CTRL */
3635#define DDRMON_CTRL 0x04
3736#define DDRMON_CTRL_LPDDR5 BIT(6)
4140#define DDRMON_CTRL_LPDDR23 BIT(2)
4241#define DDRMON_CTRL_SOFTWARE_EN BIT(1)
4342#define DDRMON_CTRL_TIMER_CNT_EN BIT(0)
44- #define DDRMON_CTRL_DDR_TYPE_MASK (DDRMON_CTRL_LPDDR5 | \
45- DDRMON_CTRL_DDR4 | \
46- DDRMON_CTRL_LPDDR4 | \
47- DDRMON_CTRL_LPDDR23)
4843#define DDRMON_CTRL_LP5_BANK_MODE_MASK GENMASK(8, 7)
4944
5045#define DDRMON_CH0_WR_NUM 0x20
@@ -124,27 +119,31 @@ struct rockchip_dfi {
124119 unsigned int count_multiplier ; /* number of data clocks per count */
125120};
126121
127- static int rockchip_dfi_ddrtype_to_ctrl (struct rockchip_dfi * dfi , u32 * ctrl ,
128- u32 * mask )
122+ static int rockchip_dfi_ddrtype_to_ctrl (struct rockchip_dfi * dfi , u32 * ctrl )
129123{
130124 u32 ddrmon_ver ;
131125
132- * mask = DDRMON_CTRL_DDR_TYPE_MASK ;
133-
134126 switch (dfi -> ddr_type ) {
135127 case ROCKCHIP_DDRTYPE_LPDDR2 :
136128 case ROCKCHIP_DDRTYPE_LPDDR3 :
137- * ctrl = DDRMON_CTRL_LPDDR23 ;
129+ * ctrl = FIELD_PREP_WM16 (DDRMON_CTRL_LPDDR23 , 1 ) |
130+ FIELD_PREP_WM16 (DDRMON_CTRL_LPDDR4 , 0 ) |
131+ FIELD_PREP_WM16 (DDRMON_CTRL_LPDDR5 , 0 );
138132 break ;
139133 case ROCKCHIP_DDRTYPE_LPDDR4 :
140134 case ROCKCHIP_DDRTYPE_LPDDR4X :
141- * ctrl = DDRMON_CTRL_LPDDR4 ;
135+ * ctrl = FIELD_PREP_WM16 (DDRMON_CTRL_LPDDR23 , 0 ) |
136+ FIELD_PREP_WM16 (DDRMON_CTRL_LPDDR4 , 1 ) |
137+ FIELD_PREP_WM16 (DDRMON_CTRL_LPDDR5 , 0 );
142138 break ;
143139 case ROCKCHIP_DDRTYPE_LPDDR5 :
144140 ddrmon_ver = readl_relaxed (dfi -> regs );
145141 if (ddrmon_ver < 0x40 ) {
146- * ctrl = DDRMON_CTRL_LPDDR5 | dfi -> lp5_bank_mode ;
147- * mask |= DDRMON_CTRL_LP5_BANK_MODE_MASK ;
142+ * ctrl = FIELD_PREP_WM16 (DDRMON_CTRL_LPDDR23 , 0 ) |
143+ FIELD_PREP_WM16 (DDRMON_CTRL_LPDDR4 , 0 ) |
144+ FIELD_PREP_WM16 (DDRMON_CTRL_LPDDR5 , 1 ) |
145+ FIELD_PREP_WM16 (DDRMON_CTRL_LP5_BANK_MODE_MASK ,
146+ dfi -> lp5_bank_mode );
148147 break ;
149148 }
150149
@@ -172,7 +171,6 @@ static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
172171 void __iomem * dfi_regs = dfi -> regs ;
173172 int i , ret = 0 ;
174173 u32 ctrl ;
175- u32 ctrl_mask ;
176174
177175 mutex_lock (& dfi -> mutex );
178176
@@ -186,7 +184,7 @@ static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
186184 goto out ;
187185 }
188186
189- ret = rockchip_dfi_ddrtype_to_ctrl (dfi , & ctrl , & ctrl_mask );
187+ ret = rockchip_dfi_ddrtype_to_ctrl (dfi , & ctrl );
190188 if (ret )
191189 goto out ;
192190
@@ -196,15 +194,16 @@ static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
196194 continue ;
197195
198196 /* clear DDRMON_CTRL setting */
199- writel_relaxed (HIWORD_UPDATE (0 , DDRMON_CTRL_TIMER_CNT_EN |
200- DDRMON_CTRL_SOFTWARE_EN | DDRMON_CTRL_HARDWARE_EN ),
197+ writel_relaxed (FIELD_PREP_WM16 (DDRMON_CTRL_TIMER_CNT_EN , 0 ) |
198+ FIELD_PREP_WM16 (DDRMON_CTRL_SOFTWARE_EN , 0 ) |
199+ FIELD_PREP_WM16 (DDRMON_CTRL_HARDWARE_EN , 0 ),
201200 dfi_regs + i * dfi -> ddrmon_stride + DDRMON_CTRL );
202201
203- writel_relaxed (HIWORD_UPDATE ( ctrl , ctrl_mask ),
204- dfi_regs + i * dfi -> ddrmon_stride + DDRMON_CTRL );
202+ writel_relaxed (ctrl , dfi_regs + i * dfi -> ddrmon_stride +
203+ DDRMON_CTRL );
205204
206205 /* enable count, use software mode */
207- writel_relaxed (HIWORD_UPDATE (DDRMON_CTRL_SOFTWARE_EN , DDRMON_CTRL_SOFTWARE_EN ),
206+ writel_relaxed (FIELD_PREP_WM16 (DDRMON_CTRL_SOFTWARE_EN , 1 ),
208207 dfi_regs + i * dfi -> ddrmon_stride + DDRMON_CTRL );
209208
210209 if (dfi -> ddrmon_ctrl_single )
@@ -234,8 +233,8 @@ static void rockchip_dfi_disable(struct rockchip_dfi *dfi)
234233 if (!(dfi -> channel_mask & BIT (i )))
235234 continue ;
236235
237- writel_relaxed (HIWORD_UPDATE ( 0 , DDRMON_CTRL_SOFTWARE_EN ),
238- dfi_regs + i * dfi -> ddrmon_stride + DDRMON_CTRL );
236+ writel_relaxed (FIELD_PREP_WM16 ( DDRMON_CTRL_SOFTWARE_EN , 0 ),
237+ dfi_regs + i * dfi -> ddrmon_stride + DDRMON_CTRL );
239238
240239 if (dfi -> ddrmon_ctrl_single )
241240 break ;
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