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dt-bindings: phy: marvell,comphy-cp110: Fix clock and child node constraints
In converting marvell,comphy-cp110 to schema, the constraints for clocks on marvell,comphy-a3700 are wrong, the maximum number of child nodes are wrong, and the phy nodes may have a 'connector' child node: phy@18300 (marvell,comphy-a3700): clock-names: False schema does not allow ['xtal'] phy@120000 (marvell,comphy-cp110): 'phy@3', 'phy@4', 'phy@5' do not match any of the regexes: '^phy@[0-2]$', '^pinctrl-[0-9]+$' phy@120000 (marvell,comphy-cp110): phy@2: 'connector' does not match any of the regexes: '^pinctrl-[0-9]+$' Fixes: 50355ac ("dt-bindings: phy: Convert marvell,comphy-cp110 to DT schema") Signed-off-by: Rob Herring (Arm) <[email protected]> Reviewed-by: Miquel Raynal <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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Documentation/devicetree/bindings/phy/marvell,comphy-cp110.yaml

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@@ -47,32 +47,34 @@ properties:
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const: 0
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clocks:
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minItems: 1
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maxItems: 3
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description: Reference clocks for CP110; MG clock, MG Core clock, AXI clock
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clock-names:
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items:
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- const: mg_clk
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- const: mg_core_clk
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- const: axi_clk
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minItems: 1
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maxItems: 3
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marvell,system-controller:
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description: Phandle to the Marvell system controller (CP110 only)
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$ref: /schemas/types.yaml#/definitions/phandle
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patternProperties:
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'^phy@[0-2]$':
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'^phy@[0-5]$':
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description: A COMPHY lane child node
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type: object
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additionalProperties: false
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properties:
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reg:
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description: COMPHY lane number
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maximum: 5
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'#phy-cells':
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const: 1
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connector:
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type: object
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required:
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- reg
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- '#phy-cells'
@@ -91,13 +93,24 @@ allOf:
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then:
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properties:
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clocks: false
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clock-names: false
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clocks:
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maxItems: 1
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clock-names:
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const: xtal
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required:
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- reg-names
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else:
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properties:
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clocks:
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minItems: 3
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clock-names:
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items:
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- const: mg_clk
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- const: mg_core_clk
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- const: axi_clk
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required:
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- marvell,system-controller
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