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Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
Pull SCSI updates from James Bottomley: "Usual driver updates (ufs, mpi3mr, lpfc, pm80xx, mpt3sas) plus assorted cleanups and fixes. The only core update is to sd.c and is mostly cosmetic" * tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi: (105 commits) scsi: MAINTAINERS: Update FC element owners scsi: mpt3sas: Update driver version to 54.100.00.00 scsi: mpt3sas: Add support for 22.5 Gbps SAS link rate scsi: mpt3sas: Suppress unnecessary IOCLogInfo on CONFIG_INVALID_PAGE scsi: mpt3sas: Fix crash in transport port remove by using ioc_info() scsi: ufs: ufs-qcom: Add support for limiting HS gear and rate scsi: ufs: pltfrm: Add DT support to limit HS gear and gear rate scsi: ufs: ufs-qcom: Remove redundant re-assignment to hs_rate scsi: ufs: dt-bindings: Document gear and rate limit properties scsi: ufs: core: Fix data race in CPU latency PM QoS request handling scsi: libfc: Fix potential buffer overflow in fc_ct_ms_fill() scsi: storvsc: Remove redundant ternary operators scsi: ufs: core: Change MCQ interrupt enable flow scsi: smartpqi: Replace kmalloc() + copy_from_user() with memdup_user() scsi: hpsa: Replace kmalloc() + copy_from_user() with memdup_user() scsi: hpsa: Fix potential memory leak in hpsa_big_passthru_ioctl() scsi: lpfc: Copyright updates for 14.4.0.11 patches scsi: lpfc: Update lpfc version to 14.4.0.11 scsi: lpfc: Convert debugfs directory counts from atomic to unsigned int scsi: lpfc: Clean up extraneous phba dentries ...
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‎Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml‎

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/ufs/qcom,sc7180-ufshc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SC7180 and Other SoCs UFS Controllers
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maintainers:
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- Bjorn Andersson <[email protected]>
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# Select only our matches, not all jedec,ufs-2.0
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select:
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properties:
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compatible:
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contains:
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enum:
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- qcom,msm8998-ufshc
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- qcom,qcs8300-ufshc
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- qcom,sa8775p-ufshc
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- qcom,sc7180-ufshc
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- qcom,sc7280-ufshc
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- qcom,sc8180x-ufshc
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- qcom,sc8280xp-ufshc
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- qcom,sm8250-ufshc
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- qcom,sm8350-ufshc
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- qcom,sm8450-ufshc
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- qcom,sm8550-ufshc
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required:
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- compatible
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properties:
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compatible:
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items:
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- enum:
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- qcom,msm8998-ufshc
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- qcom,qcs8300-ufshc
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- qcom,sa8775p-ufshc
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- qcom,sc7180-ufshc
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- qcom,sc7280-ufshc
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- qcom,sc8180x-ufshc
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- qcom,sc8280xp-ufshc
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- qcom,sm8250-ufshc
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- qcom,sm8350-ufshc
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- qcom,sm8450-ufshc
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- qcom,sm8550-ufshc
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- const: qcom,ufshc
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- const: jedec,ufs-2.0
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reg:
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maxItems: 1
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reg-names:
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items:
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- const: std
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clocks:
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minItems: 7
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maxItems: 8
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clock-names:
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minItems: 7
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items:
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- const: core_clk
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- const: bus_aggr_clk
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- const: iface_clk
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- const: core_clk_unipro
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- const: ref_clk
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- const: tx_lane0_sync_clk
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- const: rx_lane0_sync_clk
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- const: rx_lane1_sync_clk
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qcom,ice:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to the Inline Crypto Engine node
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required:
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- compatible
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- reg
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allOf:
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- $ref: qcom,ufs-common.yaml
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sc7180-ufshc
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then:
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properties:
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clocks:
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maxItems: 7
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clock-names:
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maxItems: 7
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else:
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properties:
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clocks:
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minItems: 8
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clock-names:
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minItems: 8
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sm8450.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interconnect/qcom,sm8450.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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ufs@1d84000 {
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compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
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"jedec,ufs-2.0";
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reg = <0x0 0x01d84000 0x0 0x3000>;
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interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&ufs_mem_phy_lanes>;
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phy-names = "ufsphy";
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lanes-per-direction = <2>;
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#reset-cells = <1>;
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resets = <&gcc GCC_UFS_PHY_BCR>;
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reset-names = "rst";
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reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
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vcc-supply = <&vreg_l7b_2p5>;
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vcc-max-microamp = <1100000>;
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vccq-supply = <&vreg_l9b_1p2>;
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vccq-max-microamp = <1200000>;
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power-domains = <&gcc UFS_PHY_GDSC>;
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iommus = <&apps_smmu 0xe0 0x0>;
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interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
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interconnect-names = "ufs-ddr", "cpu-ufs";
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clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
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<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
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<&gcc GCC_UFS_PHY_AHB_CLK>,
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<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
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clock-names = "core_clk",
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"bus_aggr_clk",
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"iface_clk",
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"core_clk_unipro",
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"ref_clk",
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"tx_lane0_sync_clk",
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"rx_lane0_sync_clk",
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"rx_lane1_sync_clk";
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freq-table-hz = <75000000 300000000>,
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<0 0>,
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<0 0>,
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<75000000 300000000>,
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<75000000 300000000>,
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<0 0>,
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<0 0>,
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<0 0>;
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qcom,ice = <&ice>;
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};
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};

‎Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml‎

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/ufs/qcom,sm8650-ufshc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SM8650 and Other SoCs UFS Controllers
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maintainers:
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- Bjorn Andersson <[email protected]>
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# Select only our matches, not all jedec,ufs-2.0
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select:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sm8650-ufshc
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- qcom,sm8750-ufshc
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required:
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- compatible
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properties:
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compatible:
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items:
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- enum:
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- qcom,sm8650-ufshc
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- qcom,sm8750-ufshc
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- const: qcom,ufshc
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- const: jedec,ufs-2.0
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reg:
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minItems: 1
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maxItems: 2
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reg-names:
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minItems: 1
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items:
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- const: std
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- const: mcq
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clocks:
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minItems: 8
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maxItems: 8
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clock-names:
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items:
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- const: core_clk
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- const: bus_aggr_clk
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- const: iface_clk
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- const: core_clk_unipro
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- const: ref_clk
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- const: tx_lane0_sync_clk
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- const: rx_lane0_sync_clk
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- const: rx_lane1_sync_clk
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qcom,ice:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to the Inline Crypto Engine node
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required:
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- compatible
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- reg
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allOf:
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- $ref: qcom,ufs-common.yaml
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,sm8650-gcc.h>
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#include <dt-bindings/clock/qcom,sm8650-tcsr.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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ufshc@1d84000 {
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compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
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reg = <0x0 0x01d84000 0x0 0x3000>;
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interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
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<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
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<&gcc GCC_UFS_PHY_AHB_CLK>,
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<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
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<&tcsr TCSR_UFS_PAD_CLKREF_EN>,
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<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
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clock-names = "core_clk",
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"bus_aggr_clk",
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"iface_clk",
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"core_clk_unipro",
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"ref_clk",
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"tx_lane0_sync_clk",
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"rx_lane0_sync_clk",
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"rx_lane1_sync_clk";
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resets = <&gcc GCC_UFS_PHY_BCR>;
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reset-names = "rst";
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reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
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interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
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interconnect-names = "ufs-ddr",
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"cpu-ufs";
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power-domains = <&gcc UFS_PHY_GDSC>;
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required-opps = <&rpmhpd_opp_nom>;
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operating-points-v2 = <&ufs_opp_table>;
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iommus = <&apps_smmu 0x60 0>;
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lanes-per-direction = <2>;
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qcom,ice = <&ice>;
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phys = <&ufs_mem_phy>;
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phy-names = "ufsphy";
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#reset-cells = <1>;
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vcc-supply = <&vreg_l7b_2p5>;
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vcc-max-microamp = <1100000>;
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vccq-supply = <&vreg_l9b_1p2>;
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vccq-max-microamp = <1200000>;
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ufs_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>,
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/bits/ 64 <0>,
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/bits/ 64 <0>,
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/bits/ 64 <100000000>,
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/bits/ 64 <0>,
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/bits/ 64 <0>,
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/bits/ 64 <0>,
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/bits/ 64 <0>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-201500000 {
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opp-hz = /bits/ 64 <201500000>,
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/bits/ 64 <0>,
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/bits/ 64 <0>,
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/bits/ 64 <201500000>,
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/bits/ 64 <0>,
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/bits/ 64 <0>,
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/bits/ 64 <0>,
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/bits/ 64 <0>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-403000000 {
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opp-hz = /bits/ 64 <403000000>,
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/bits/ 64 <0>,
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/bits/ 64 <0>,
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/bits/ 64 <403000000>,
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/bits/ 64 <0>,
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/bits/ 64 <0>,
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/bits/ 64 <0>,
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/bits/ 64 <0>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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};
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};
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};

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