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bebarinobebarino
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Merge branches 'clk-cleanup', 'clk-renesas', 'clk-mediatek', 'clk-samsung' and 'clk-socfpga' into clk-next
 - Support for 5L35023 variant of Versa 3 clock generator * clk-cleanup: clk: analogbits: Fix incorrect calculation of vco rate delta clk: Use str_enable_disable-like helpers clk: clk-loongson2: Switch to use devm_clk_hw_register_fixed_rate_parent_data() clk: starfive: Make _clk_get become a common helper function clk: ep93xx: make const read-only arrays static clk: lmk04832: make read-only const arrays static clk: ti: use kcalloc() instead of kzalloc() dt-bindings: clock: st,stm32mp1-rcc: complete the reference path dt-bindings: clock: st,stm32mp1-rcc: fix reference paths dt-bindings: clock: ti: Convert composite.txt to json-schema dt-bindings: clock: ti: Convert gate.txt to json-schema clk: Drop obsolete devm_clk_bulk_get_all_enable() helper PCI: exynos: Switch to devm_clk_bulk_get_all_enabled() soc: mediatek: pwrap: Switch to devm_clk_bulk_get_all_enabled() clk: davinci: remove platform data struct clk: fix an OF node reference leak in of_clk_get_parent_name() clk: mmp: pxa1908-apbc: Fix NULL vs IS_ERR() check clk: mmp: pxa1908-apbcp: Fix a NULL vs IS_ERR() check clk: mmp: pxa1908-mpmu: Fix a NULL vs IS_ERR() check * clk-renesas: (24 commits) dt-bindings: clock: renesas,r9a08g045-vbattb: Fix include guard clk: renesas: r9a09g057: Add clock and reset entries for GIC clk: renesas: r9a09g057: Add reset entry for SYS clk: renesas: r8a779g0: Add VSPX clocks clk: renesas: r8a779g0: Add FCPVX clocks clk: renesas: r9a09g047: Add I2C clocks/resets clk: renesas: r9a09g047: Add CA55 core clocks clk: renesas: rzv2h: Add support for RZ/G3E SoC clk: renesas: rzv2h: Add MSTOP support dt-bindings: clock: renesas: Document RZ/G3E SoC CPG dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants clk: versaclock3: Add support for the 5L35023 variant dt-bindings: clock: versaclock3: Document 5L35023 Versa3 clock generator clk: versaclock3: Prepare for the addition of 5L35023 device clk: renesas: r9a08g045: Add clocks, resets and power domain support for the ADC IP clk: renesas: r8a779h0: Add display clocks clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets clk: renesas: rzv2h: Add selective Runtime PM support for clocks clk: renesas: r9a06g032: Use BIT macro consistently ... * clk-mediatek: clk: ralink: mtmips: remove duplicated 'xtal' clock for Ralink SoC RT3883 clk: mediatek: mt2701-img: add missing dummy clk clk: mediatek: mt2701-mm: add missing dummy clk clk: mediatek: mt2701-bdp: add missing dummy clk clk: mediatek: mt2701-aud: fix conversion to mtk_clk_simple_probe clk: mediatek: mt2701-vdec: fix conversion to mtk_clk_simple_probe * clk-samsung: clk: samsung: Introduce Exynos990 clock controller driver clk: samsung: clk-pll: Add support for pll_{0717x, 0718x, 0732x} dt-bindings: clock: samsung: Add Exynos990 SoC CMU bindings * clk-socfpga: clk: socfpga: arria10: Optimize local variables in clk_pll_recalc_rate()
5 parents d7f1285 + 83f6c3d + 830d806 + 9c2fb0c + e9f7da0 commit 70741cc

30 files changed

+2419
-103
lines changed

‎Documentation/devicetree/bindings/clock/renesas,5p35023.yaml‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@ description: |
3131
properties:
3232
compatible:
3333
enum:
34+
- renesas,5l35023
3435
- renesas,5p35023
3536

3637
reg:

‎Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml‎

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4,19 +4,22 @@
44
$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
55
$schema: http://devicetree.org/meta-schemas/core.yaml#
66

7-
title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
7+
title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)
88

99
maintainers:
1010
- Lad Prabhakar <[email protected]>
1111

1212
description:
13-
On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
14-
and control of clock signals for the IP modules, generation and control of resets,
15-
and control over booting, low power consumption and power supply domains.
13+
On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles
14+
generation and control of clock signals for the IP modules, generation and
15+
control of resets, and control over booting, low power consumption and power
16+
supply domains.
1617

1718
properties:
1819
compatible:
19-
const: renesas,r9a09g057-cpg
20+
enum:
21+
- renesas,r9a09g047-cpg # RZ/G3E
22+
- renesas,r9a09g057-cpg # RZ/V2H
2023

2124
reg:
2225
maxItems: 1
@@ -37,7 +40,7 @@ properties:
3740
description: |
3841
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
3942
and a core clock reference, as defined in
40-
<dt-bindings/clock/renesas,r9a09g057-cpg.h>,
43+
<dt-bindings/clock/renesas,r9a09g0*-cpg.h>,
4144
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
4245
a module number. The module number is calculated as the CLKON register
4346
offset index multiplied by 16, plus the actual bit in the register

‎Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml‎

Lines changed: 121 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,121 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/clock/samsung,exynos990-clock.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Samsung Exynos990 SoC clock controller
8+
9+
maintainers:
10+
- Igor Belwon <[email protected]>
11+
- Chanwoo Choi <[email protected]>
12+
- Krzysztof Kozlowski <[email protected]>
13+
14+
description: |
15+
Exynos990 clock controller is comprised of several CMU units, generating
16+
clocks for different domains. Those CMU units are modeled as separate device
17+
tree nodes, and might depend on each other. The root clock in that root tree
18+
is an external clock: OSCCLK (26 MHz). This external clock must be defined
19+
as a fixed-rate clock in dts.
20+
21+
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
22+
dividers; all other clocks of function blocks (other CMUs) are usually
23+
derived from CMU_TOP.
24+
25+
Each clock is assigned an identifier and client nodes can use this identifier
26+
to specify the clock which they consume. All clocks available for usage
27+
in clock consumer nodes are defined as preprocessor macros in
28+
'include/dt-bindings/clock/samsung,exynos990.h' header.
29+
30+
properties:
31+
compatible:
32+
enum:
33+
- samsung,exynos990-cmu-hsi0
34+
- samsung,exynos990-cmu-top
35+
36+
clocks:
37+
minItems: 1
38+
maxItems: 5
39+
40+
clock-names:
41+
minItems: 1
42+
maxItems: 5
43+
44+
"#clock-cells":
45+
const: 1
46+
47+
reg:
48+
maxItems: 1
49+
50+
required:
51+
- compatible
52+
- clocks
53+
- clock-names
54+
- "#clock-cells"
55+
- reg
56+
57+
allOf:
58+
- if:
59+
properties:
60+
compatible:
61+
contains:
62+
const: samsung,exynos990-cmu-hsi0
63+
64+
then:
65+
properties:
66+
clocks:
67+
items:
68+
- description: External reference clock (26 MHz)
69+
- description: CMU_HSI0 BUS clock (from CMU_TOP)
70+
- description: CMU_HSI0 USB31DRD clock (from CMU_TOP)
71+
- description: CMU_HSI0 USBDP_DEBUG clock (from CMU_TOP)
72+
- description: CMU_HSI0 DPGTC clock (from CMU_TOP)
73+
74+
clock-names:
75+
items:
76+
- const: oscclk
77+
- const: bus
78+
- const: usb31drd
79+
- const: usbdp_debug
80+
- const: dpgtc
81+
82+
- if:
83+
properties:
84+
compatible:
85+
contains:
86+
const: samsung,exynos990-cmu-top
87+
88+
then:
89+
properties:
90+
clocks:
91+
items:
92+
- description: External reference clock (26 MHz)
93+
94+
clock-names:
95+
items:
96+
- const: oscclk
97+
98+
additionalProperties: false
99+
100+
examples:
101+
- |
102+
#include <dt-bindings/clock/samsung,exynos990.h>
103+
104+
cmu_hsi0: clock-controller@10a00000 {
105+
compatible = "samsung,exynos990-cmu-hsi0";
106+
reg = <0x10a00000 0x8000>;
107+
#clock-cells = <1>;
108+
109+
clocks = <&oscclk>,
110+
<&cmu_top CLK_DOUT_CMU_HSI0_BUS>,
111+
<&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>,
112+
<&cmu_top CLK_DOUT_CMU_HSI0_USBDP_DEBUG>,
113+
<&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>;
114+
clock-names = "oscclk",
115+
"bus",
116+
"usb31drd",
117+
"usbdp_debug",
118+
"dpgtc";
119+
};
120+
121+
...

‎Documentation/devicetree/bindings/soc/renesas/renesas.yaml‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -525,6 +525,23 @@ properties:
525525
- renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0
526526
- const: renesas,r9a09g011
527527

528+
- description: RZ/G3E (R9A09G047)
529+
items:
530+
- enum:
531+
- renesas,smarc2-evk # RZ SMARC Carrier-II EVK
532+
- enum:
533+
- renesas,rzg3e-smarcm # RZ/G3E SMARC Module (SoM)
534+
- enum:
535+
- renesas,r9a09g047e27 # Dual Cortex-A55 + Cortex-M33 (15mm BGA)
536+
- renesas,r9a09g047e28 # Dual Cortex-A55 + Cortex-M33 (21mm BGA)
537+
- renesas,r9a09g047e37 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)
538+
- renesas,r9a09g047e38 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
539+
- renesas,r9a09g047e47 # Quad Cortex-A55 + Cortex-M33 (15mm BGA)
540+
- renesas,r9a09g047e48 # Quad Cortex-A55 + Cortex-M33 (21mm BGA)
541+
- renesas,r9a09g047e57 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)
542+
- renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
543+
- const: renesas,r9a09g047
544+
528545
- description: RZ/V2H(P) (R9A09G057)
529546
items:
530547
- enum:

‎drivers/clk/clk-versaclock3.c‎

Lines changed: 49 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -78,9 +78,6 @@
7878
#define VC3_PLL1_VCO_MIN 300000000UL
7979
#define VC3_PLL1_VCO_MAX 600000000UL
8080

81-
#define VC3_PLL2_VCO_MIN 400000000UL
82-
#define VC3_PLL2_VCO_MAX 1200000000UL
83-
8481
#define VC3_PLL3_VCO_MIN 300000000UL
8582
#define VC3_PLL3_VCO_MAX 800000000UL
8683

@@ -147,9 +144,13 @@ struct vc3_pfd_data {
147144
u8 mdiv2_bitmsk;
148145
};
149146

147+
struct vc3_vco {
148+
unsigned long min;
149+
unsigned long max;
150+
};
151+
150152
struct vc3_pll_data {
151-
unsigned long vco_min;
152-
unsigned long vco_max;
153+
struct vc3_vco vco;
153154
u8 num;
154155
u8 int_div_msb_offs;
155156
u8 int_div_lsb_offs;
@@ -166,12 +167,17 @@ struct vc3_div_data {
166167
struct vc3_hw_data {
167168
struct clk_hw hw;
168169
struct regmap *regmap;
169-
const void *data;
170+
void *data;
170171

171172
u32 div_int;
172173
u32 div_frc;
173174
};
174175

176+
struct vc3_hw_cfg {
177+
struct vc3_vco pll2_vco;
178+
u32 se2_clk_sel_msk;
179+
};
180+
175181
static const struct clk_div_table div1_divs[] = {
176182
{ .val = 0, .div = 1, }, { .val = 1, .div = 4, },
177183
{ .val = 2, .div = 5, }, { .val = 3, .div = 6, },
@@ -386,10 +392,10 @@ static long vc3_pll_round_rate(struct clk_hw *hw, unsigned long rate,
386392
const struct vc3_pll_data *pll = vc3->data;
387393
u64 div_frc;
388394

389-
if (rate < pll->vco_min)
390-
rate = pll->vco_min;
391-
if (rate > pll->vco_max)
392-
rate = pll->vco_max;
395+
if (rate < pll->vco.min)
396+
rate = pll->vco.min;
397+
if (rate > pll->vco.max)
398+
rate = pll->vco.max;
393399

394400
vc3->div_int = rate / *parent_rate;
395401

@@ -680,8 +686,10 @@ static struct vc3_hw_data clk_pll[] = {
680686
.num = VC3_PLL1,
681687
.int_div_msb_offs = VC3_PLL1_LOOP_FILTER_N_DIV_MSB,
682688
.int_div_lsb_offs = VC3_PLL1_VCO_N_DIVIDER,
683-
.vco_min = VC3_PLL1_VCO_MIN,
684-
.vco_max = VC3_PLL1_VCO_MAX
689+
.vco = {
690+
.min = VC3_PLL1_VCO_MIN,
691+
.max = VC3_PLL1_VCO_MAX
692+
}
685693
},
686694
.hw.init = &(struct clk_init_data) {
687695
.name = "pll1",
@@ -698,8 +706,6 @@ static struct vc3_hw_data clk_pll[] = {
698706
.num = VC3_PLL2,
699707
.int_div_msb_offs = VC3_PLL2_FB_INT_DIV_MSB,
700708
.int_div_lsb_offs = VC3_PLL2_FB_INT_DIV_LSB,
701-
.vco_min = VC3_PLL2_VCO_MIN,
702-
.vco_max = VC3_PLL2_VCO_MAX
703709
},
704710
.hw.init = &(struct clk_init_data) {
705711
.name = "pll2",
@@ -716,8 +722,10 @@ static struct vc3_hw_data clk_pll[] = {
716722
.num = VC3_PLL3,
717723
.int_div_msb_offs = VC3_PLL3_LOOP_FILTER_N_DIV_MSB,
718724
.int_div_lsb_offs = VC3_PLL3_N_DIVIDER,
719-
.vco_min = VC3_PLL3_VCO_MIN,
720-
.vco_max = VC3_PLL3_VCO_MAX
725+
.vco = {
726+
.min = VC3_PLL3_VCO_MIN,
727+
.max = VC3_PLL3_VCO_MAX
728+
}
721729
},
722730
.hw.init = &(struct clk_init_data) {
723731
.name = "pll3",
@@ -901,7 +909,6 @@ static struct vc3_hw_data clk_mux[] = {
901909
[VC3_SE2_MUX] = {
902910
.data = &(struct vc3_clk_data) {
903911
.offs = VC3_SE2_CTRL_REG0,
904-
.bitmsk = VC3_SE2_CTRL_REG0_SE2_CLK_SEL
905912
},
906913
.hw.init = &(struct clk_init_data) {
907914
.name = "se2_mux",
@@ -982,6 +989,7 @@ static int vc3_probe(struct i2c_client *client)
982989
{
983990
struct device *dev = &client->dev;
984991
u8 settings[NUM_CONFIG_REGISTERS];
992+
const struct vc3_hw_cfg *data;
985993
struct regmap *regmap;
986994
const char *name;
987995
int ret, i;
@@ -1029,9 +1037,16 @@ static int vc3_probe(struct i2c_client *client)
10291037
clk_pfd[i].hw.init->name);
10301038
}
10311039

1040+
data = i2c_get_match_data(client);
1041+
10321042
/* Register pll's */
10331043
for (i = 0; i < ARRAY_SIZE(clk_pll); i++) {
10341044
clk_pll[i].regmap = regmap;
1045+
if (i == VC3_PLL2) {
1046+
struct vc3_pll_data *pll_data = clk_pll[i].data;
1047+
1048+
pll_data->vco = data->pll2_vco;
1049+
}
10351050
ret = devm_clk_hw_register(dev, &clk_pll[i].hw);
10361051
if (ret)
10371052
return dev_err_probe(dev, ret, "%s failed\n",
@@ -1059,6 +1074,11 @@ static int vc3_probe(struct i2c_client *client)
10591074
/* Register clk muxes */
10601075
for (i = 0; i < ARRAY_SIZE(clk_mux); i++) {
10611076
clk_mux[i].regmap = regmap;
1077+
if (i == VC3_SE2_MUX) {
1078+
struct vc3_clk_data *clk_data = clk_mux[i].data;
1079+
1080+
clk_data->bitmsk = data->se2_clk_sel_msk;
1081+
}
10621082
ret = devm_clk_hw_register(dev, &clk_mux[i].hw);
10631083
if (ret)
10641084
return dev_err_probe(dev, ret, "%s failed\n",
@@ -1108,8 +1128,19 @@ static int vc3_probe(struct i2c_client *client)
11081128
return ret;
11091129
}
11101130

1131+
static const struct vc3_hw_cfg vc3_5p = {
1132+
.pll2_vco = { .min = 400000000UL, .max = 1200000000UL },
1133+
.se2_clk_sel_msk = BIT(6),
1134+
};
1135+
1136+
static const struct vc3_hw_cfg vc3_5l = {
1137+
.pll2_vco = { .min = 30000000UL, .max = 130000000UL },
1138+
.se2_clk_sel_msk = BIT(0),
1139+
};
1140+
11111141
static const struct of_device_id dev_ids[] = {
1112-
{ .compatible = "renesas,5p35023" },
1142+
{ .compatible = "renesas,5p35023", .data = &vc3_5p },
1143+
{ .compatible = "renesas,5l35023", .data = &vc3_5l },
11131144
{ /* Sentinel */ }
11141145
};
11151146
MODULE_DEVICE_TABLE(of, dev_ids);

‎drivers/clk/mediatek/clk-mt2701-aud.c‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -55,10 +55,16 @@ static const struct mtk_gate audio_clks[] = {
5555
GATE_DUMMY(CLK_DUMMY, "aud_dummy"),
5656
/* AUDIO0 */
5757
GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2),
58+
GATE_DUMMY(CLK_AUD_LRCK_DETECT, "audio_lrck_detect_dummy"),
59+
GATE_DUMMY(CLK_AUD_I2S, "audio_i2c_dummy"),
60+
GATE_DUMMY(CLK_AUD_APLL_TUNER, "audio_apll_tuner_dummy"),
5861
GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20),
5962
GATE_AUDIO0(CLK_AUD_SPDF, "audio_spdf", "audpll_sel", 21),
6063
GATE_AUDIO0(CLK_AUD_SPDF2, "audio_spdf2", "audpll_sel", 22),
6164
GATE_AUDIO0(CLK_AUD_APLL, "audio_apll", "audpll_sel", 23),
65+
GATE_DUMMY(CLK_AUD_TML, "audio_tml_dummy"),
66+
GATE_DUMMY(CLK_AUD_AHB_IDLE_EXT, "audio_ahb_idle_ext_dummy"),
67+
GATE_DUMMY(CLK_AUD_AHB_IDLE_INT, "audio_ahb_idle_int_dummy"),
6268
/* AUDIO1 */
6369
GATE_AUDIO1(CLK_AUD_I2SIN1, "audio_i2sin1", "aud_mux1_sel", 0),
6470
GATE_AUDIO1(CLK_AUD_I2SIN2, "audio_i2sin2", "aud_mux1_sel", 1),
@@ -76,10 +82,12 @@ static const struct mtk_gate audio_clks[] = {
7682
GATE_AUDIO1(CLK_AUD_ASRCI2, "audio_asrci2", "asm_h_sel", 13),
7783
GATE_AUDIO1(CLK_AUD_ASRCO1, "audio_asrco1", "asm_h_sel", 14),
7884
GATE_AUDIO1(CLK_AUD_ASRCO2, "audio_asrco2", "asm_h_sel", 15),
85+
GATE_DUMMY(CLK_AUD_HDMIRX, "audio_hdmirx_dummy"),
7986
GATE_AUDIO1(CLK_AUD_INTDIR, "audio_intdir", "intdir_sel", 20),
8087
GATE_AUDIO1(CLK_AUD_A1SYS, "audio_a1sys", "aud_mux1_sel", 21),
8188
GATE_AUDIO1(CLK_AUD_A2SYS, "audio_a2sys", "aud_mux2_sel", 22),
8289
GATE_AUDIO1(CLK_AUD_AFE_CONN, "audio_afe_conn", "aud_mux1_sel", 23),
90+
GATE_DUMMY(CLK_AUD_AFE_PCMIF, "audio_afe_pcmif_dummy"),
8391
GATE_AUDIO1(CLK_AUD_AFE_MRGIF, "audio_afe_mrgif", "aud_mux1_sel", 25),
8492
/* AUDIO2 */
8593
GATE_AUDIO2(CLK_AUD_MMIF_UL1, "audio_ul1", "aud_mux1_sel", 0),
@@ -100,6 +108,8 @@ static const struct mtk_gate audio_clks[] = {
100108
GATE_AUDIO2(CLK_AUD_MMIF_AWB2, "audio_awb2", "aud_mux1_sel", 15),
101109
GATE_AUDIO2(CLK_AUD_MMIF_DAI, "audio_dai", "aud_mux1_sel", 16),
102110
/* AUDIO3 */
111+
GATE_DUMMY(CLK_AUD_DMIC1, "audio_dmic1_dummy"),
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GATE_DUMMY(CLK_AUD_DMIC2, "audio_dmic2_dummy"),
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GATE_AUDIO3(CLK_AUD_ASRCI3, "audio_asrci3", "asm_h_sel", 2),
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GATE_AUDIO3(CLK_AUD_ASRCI4, "audio_asrci4", "asm_h_sel", 3),
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GATE_AUDIO3(CLK_AUD_ASRCI5, "audio_asrci5", "asm_h_sel", 4),

‎drivers/clk/mediatek/clk-mt2701-bdp.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@ static const struct mtk_gate_regs bdp1_cg_regs = {
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GATE_MTK(_id, _name, _parent, &bdp1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
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static const struct mtk_gate bdp_clks[] = {
34+
GATE_DUMMY(CLK_DUMMY, "bdp_dummy"),
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GATE_BDP0(CLK_BDP_BRG_BA, "brg_baclk", "mm_sel", 0),
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GATE_BDP0(CLK_BDP_BRG_DRAM, "brg_dram", "mm_sel", 1),
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GATE_BDP0(CLK_BDP_LARB_DRAM, "larb_dram", "mm_sel", 2),

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