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kuba-mookuba-moo
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Merge branch 'net-stmmac-ingenic-convert-to-set_phy_intf_sel'
Russell King says: ==================== net: stmmac: ingenic: convert to set_phy_intf_sel() Convert ingenic to use the new ->set_phy_intf_sel() method that was recently introduced in net-next. This is the largest of the conversions, as there is scope for cleanups along with the conversion. ==================== Link: https://patch.msgid.link/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2 parents 7ff14c5 + 34bf68a commit 71bc986

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+45
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‎drivers/net/ethernet/stmicro/stmmac/dwmac-ingenic.c‎

Lines changed: 45 additions & 120 deletions
Original file line numberDiff line numberDiff line change
@@ -35,10 +35,6 @@
3535
#define MACPHYC_RX_DELAY_MASK GENMASK(10, 4)
3636
#define MACPHYC_SOFT_RST_MASK GENMASK(3, 3)
3737
#define MACPHYC_PHY_INFT_MASK GENMASK(2, 0)
38-
#define MACPHYC_PHY_INFT_RMII 0x4
39-
#define MACPHYC_PHY_INFT_RGMII 0x1
40-
#define MACPHYC_PHY_INFT_GMII 0x0
41-
#define MACPHYC_PHY_INFT_MII 0x0
4238

4339
#define MACPHYC_TX_DELAY_PS_MAX 2496
4440
#define MACPHYC_TX_DELAY_PS_MIN 20
@@ -68,172 +64,93 @@ struct ingenic_soc_info {
6864
enum ingenic_mac_version version;
6965
u32 mask;
7066

71-
int (*set_mode)(struct plat_stmmacenet_data *plat_dat);
72-
};
73-
74-
static int ingenic_mac_init(struct platform_device *pdev, void *bsp_priv)
75-
{
76-
struct ingenic_mac *mac = bsp_priv;
77-
int ret;
67+
int (*set_mode)(struct ingenic_mac *mac, u8 phy_intf_sel);
7868

79-
if (mac->soc_info->set_mode) {
80-
ret = mac->soc_info->set_mode(mac->plat_dat);
81-
if (ret)
82-
return ret;
83-
}
84-
85-
return 0;
86-
}
69+
u8 valid_phy_intf_sel;
70+
};
8771

88-
static int jz4775_mac_set_mode(struct plat_stmmacenet_data *plat_dat)
72+
static int jz4775_mac_set_mode(struct ingenic_mac *mac, u8 phy_intf_sel)
8973
{
90-
struct ingenic_mac *mac = plat_dat->bsp_priv;
9174
unsigned int val;
9275

93-
switch (plat_dat->phy_interface) {
94-
case PHY_INTERFACE_MODE_MII:
95-
val = FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, MACPHYC_TXCLK_SEL_INPUT) |
96-
FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_MII);
97-
dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_MII\n");
98-
break;
99-
100-
case PHY_INTERFACE_MODE_GMII:
101-
val = FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, MACPHYC_TXCLK_SEL_INPUT) |
102-
FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_GMII);
103-
dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_GMII\n");
104-
break;
105-
106-
case PHY_INTERFACE_MODE_RMII:
107-
val = FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, MACPHYC_TXCLK_SEL_INPUT) |
108-
FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RMII);
109-
dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");
110-
break;
111-
112-
case PHY_INTERFACE_MODE_RGMII:
113-
case PHY_INTERFACE_MODE_RGMII_ID:
114-
case PHY_INTERFACE_MODE_RGMII_TXID:
115-
case PHY_INTERFACE_MODE_RGMII_RXID:
116-
val = FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, MACPHYC_TXCLK_SEL_INPUT) |
117-
FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RGMII);
118-
dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RGMII\n");
119-
break;
120-
121-
default:
122-
dev_err(mac->dev, "Unsupported interface %s\n",
123-
phy_modes(plat_dat->phy_interface));
124-
return -EINVAL;
125-
}
76+
val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, phy_intf_sel) |
77+
FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, MACPHYC_TXCLK_SEL_INPUT);
12678

12779
/* Update MAC PHY control register */
12880
return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, val);
12981
}
13082

131-
static int x1000_mac_set_mode(struct plat_stmmacenet_data *plat_dat)
83+
static int x1000_mac_set_mode(struct ingenic_mac *mac, u8 phy_intf_sel)
13284
{
133-
struct ingenic_mac *mac = plat_dat->bsp_priv;
134-
135-
switch (plat_dat->phy_interface) {
136-
case PHY_INTERFACE_MODE_RMII:
137-
dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");
138-
break;
139-
140-
default:
141-
dev_err(mac->dev, "Unsupported interface %s\n",
142-
phy_modes(plat_dat->phy_interface));
143-
return -EINVAL;
144-
}
145-
14685
/* Update MAC PHY control register */
14786
return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, 0);
14887
}
14988

150-
static int x1600_mac_set_mode(struct plat_stmmacenet_data *plat_dat)
89+
static int x1600_mac_set_mode(struct ingenic_mac *mac, u8 phy_intf_sel)
15190
{
152-
struct ingenic_mac *mac = plat_dat->bsp_priv;
15391
unsigned int val;
15492

155-
switch (plat_dat->phy_interface) {
156-
case PHY_INTERFACE_MODE_RMII:
157-
val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RMII);
158-
dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");
159-
break;
160-
161-
default:
162-
dev_err(mac->dev, "Unsupported interface %s\n",
163-
phy_modes(plat_dat->phy_interface));
164-
return -EINVAL;
165-
}
93+
val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, phy_intf_sel);
16694

16795
/* Update MAC PHY control register */
16896
return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, val);
16997
}
17098

171-
static int x1830_mac_set_mode(struct plat_stmmacenet_data *plat_dat)
99+
static int x1830_mac_set_mode(struct ingenic_mac *mac, u8 phy_intf_sel)
172100
{
173-
struct ingenic_mac *mac = plat_dat->bsp_priv;
174101
unsigned int val;
175102

176-
switch (plat_dat->phy_interface) {
177-
case PHY_INTERFACE_MODE_RMII:
178-
val = FIELD_PREP(MACPHYC_MODE_SEL_MASK, MACPHYC_MODE_SEL_RMII) |
179-
FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RMII);
180-
dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");
181-
break;
182-
183-
default:
184-
dev_err(mac->dev, "Unsupported interface %s\n",
185-
phy_modes(plat_dat->phy_interface));
186-
return -EINVAL;
187-
}
103+
val = FIELD_PREP(MACPHYC_MODE_SEL_MASK, MACPHYC_MODE_SEL_RMII) |
104+
FIELD_PREP(MACPHYC_PHY_INFT_MASK, phy_intf_sel);
188105

189106
/* Update MAC PHY control register */
190107
return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, val);
191108
}
192109

193-
static int x2000_mac_set_mode(struct plat_stmmacenet_data *plat_dat)
110+
static int x2000_mac_set_mode(struct ingenic_mac *mac, u8 phy_intf_sel)
194111
{
195-
struct ingenic_mac *mac = plat_dat->bsp_priv;
196112
unsigned int val;
197113

198-
switch (plat_dat->phy_interface) {
199-
case PHY_INTERFACE_MODE_RMII:
200-
val = FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_ORIGIN) |
201-
FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_ORIGIN) |
202-
FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RMII);
203-
dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");
204-
break;
205-
206-
case PHY_INTERFACE_MODE_RGMII:
207-
case PHY_INTERFACE_MODE_RGMII_ID:
208-
case PHY_INTERFACE_MODE_RGMII_TXID:
209-
case PHY_INTERFACE_MODE_RGMII_RXID:
210-
val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RGMII);
114+
val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, phy_intf_sel);
211115

116+
if (phy_intf_sel == PHY_INTF_SEL_RMII) {
117+
val |= FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_ORIGIN) |
118+
FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_ORIGIN);
119+
} else if (phy_intf_sel == PHY_INTF_SEL_RGMII) {
212120
if (mac->tx_delay == 0)
213121
val |= FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_ORIGIN);
214122
else
215123
val |= FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_DELAY) |
216-
FIELD_PREP(MACPHYC_TX_DELAY_MASK, (mac->tx_delay + 9750) / 19500 - 1);
124+
FIELD_PREP(MACPHYC_TX_DELAY_MASK, (mac->tx_delay + 9750) / 19500 - 1);
217125

218126
if (mac->rx_delay == 0)
219127
val |= FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_ORIGIN);
220128
else
221129
val |= FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_DELAY) |
222130
FIELD_PREP(MACPHYC_RX_DELAY_MASK, (mac->rx_delay + 9750) / 19500 - 1);
223-
224-
dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RGMII\n");
225-
break;
226-
227-
default:
228-
dev_err(mac->dev, "Unsupported interface %s\n",
229-
phy_modes(plat_dat->phy_interface));
230-
return -EINVAL;
231131
}
232132

233133
/* Update MAC PHY control register */
234134
return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, val);
235135
}
236136

137+
static int ingenic_set_phy_intf_sel(void *bsp_priv, u8 phy_intf_sel)
138+
{
139+
struct ingenic_mac *mac = bsp_priv;
140+
141+
if (!mac->soc_info->set_mode)
142+
return 0;
143+
144+
if (phy_intf_sel >= BITS_PER_BYTE ||
145+
~mac->soc_info->valid_phy_intf_sel & BIT(phy_intf_sel))
146+
return -EINVAL;
147+
148+
dev_dbg(mac->dev, "MAC PHY control register: interface %s\n",
149+
phy_modes(mac->plat_dat->phy_interface));
150+
151+
return mac->soc_info->set_mode(mac, phy_intf_sel);
152+
}
153+
237154
static int ingenic_mac_probe(struct platform_device *pdev)
238155
{
239156
struct plat_stmmacenet_data *plat_dat;
@@ -293,7 +210,7 @@ static int ingenic_mac_probe(struct platform_device *pdev)
293210
mac->plat_dat = plat_dat;
294211

295212
plat_dat->bsp_priv = mac;
296-
plat_dat->init = ingenic_mac_init;
213+
plat_dat->set_phy_intf_sel = ingenic_set_phy_intf_sel;
297214

298215
return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
299216
}
@@ -303,27 +220,33 @@ static struct ingenic_soc_info jz4775_soc_info = {
303220
.mask = MACPHYC_TXCLK_SEL_MASK | MACPHYC_SOFT_RST_MASK | MACPHYC_PHY_INFT_MASK,
304221

305222
.set_mode = jz4775_mac_set_mode,
223+
.valid_phy_intf_sel = BIT(PHY_INTF_SEL_GMII_MII) |
224+
BIT(PHY_INTF_SEL_RGMII) |
225+
BIT(PHY_INTF_SEL_RMII),
306226
};
307227

308228
static struct ingenic_soc_info x1000_soc_info = {
309229
.version = ID_X1000,
310230
.mask = MACPHYC_SOFT_RST_MASK,
311231

312232
.set_mode = x1000_mac_set_mode,
233+
.valid_phy_intf_sel = BIT(PHY_INTF_SEL_RMII),
313234
};
314235

315236
static struct ingenic_soc_info x1600_soc_info = {
316237
.version = ID_X1600,
317238
.mask = MACPHYC_SOFT_RST_MASK | MACPHYC_PHY_INFT_MASK,
318239

319240
.set_mode = x1600_mac_set_mode,
241+
.valid_phy_intf_sel = BIT(PHY_INTF_SEL_RMII),
320242
};
321243

322244
static struct ingenic_soc_info x1830_soc_info = {
323245
.version = ID_X1830,
324246
.mask = MACPHYC_MODE_SEL_MASK | MACPHYC_SOFT_RST_MASK | MACPHYC_PHY_INFT_MASK,
325247

326248
.set_mode = x1830_mac_set_mode,
249+
.valid_phy_intf_sel = BIT(PHY_INTF_SEL_RMII),
327250
};
328251

329252
static struct ingenic_soc_info x2000_soc_info = {
@@ -332,6 +255,8 @@ static struct ingenic_soc_info x2000_soc_info = {
332255
MACPHYC_RX_DELAY_MASK | MACPHYC_SOFT_RST_MASK | MACPHYC_PHY_INFT_MASK,
333256

334257
.set_mode = x2000_mac_set_mode,
258+
.valid_phy_intf_sel = BIT(PHY_INTF_SEL_RGMII) |
259+
BIT(PHY_INTF_SEL_RMII),
335260
};
336261

337262
static const struct of_device_id ingenic_mac_of_matches[] = {

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