@@ -244,6 +244,13 @@ static struct clk_bulk_data exynos5433_clk_bulk_data[] = {
244244 { .id = "sclk_rgb_vclk_to_dsim0" },
245245};
246246
247+ static struct clk_bulk_data exynos7870_clk_bulk_data [] = {
248+ { .id = "bus" },
249+ { .id = "pll" },
250+ { .id = "byte" },
251+ { .id = "esc" },
252+ };
253+
247254enum reg_idx {
248255 DSIM_STATUS_REG , /* Status register (legacy) */
249256 DSIM_LINK_STATUS_REG , /* Link status register */
@@ -320,6 +327,32 @@ static const unsigned int exynos5433_reg_ofs[] = {
320327 [DSIM_PHYTIMING2_REG ] = 0xBC ,
321328};
322329
330+ static const unsigned int exynos7870_reg_ofs [] = {
331+ [DSIM_LINK_STATUS_REG ] = 0x04 ,
332+ [DSIM_DPHY_STATUS_REG ] = 0x08 ,
333+ [DSIM_SWRST_REG ] = 0x0C ,
334+ [DSIM_CLKCTRL_REG ] = 0x10 ,
335+ [DSIM_TIMEOUT_REG ] = 0x14 ,
336+ [DSIM_ESCMODE_REG ] = 0x1C ,
337+ [DSIM_MDRESOL_REG ] = 0x20 ,
338+ [DSIM_MVPORCH_REG ] = 0x24 ,
339+ [DSIM_MHPORCH_REG ] = 0x28 ,
340+ [DSIM_MSYNC_REG ] = 0x2C ,
341+ [DSIM_CONFIG_REG ] = 0x30 ,
342+ [DSIM_INTSRC_REG ] = 0x34 ,
343+ [DSIM_INTMSK_REG ] = 0x38 ,
344+ [DSIM_PKTHDR_REG ] = 0x3C ,
345+ [DSIM_PAYLOAD_REG ] = 0x40 ,
346+ [DSIM_RXFIFO_REG ] = 0x44 ,
347+ [DSIM_SFRCTRL_REG ] = 0x48 ,
348+ [DSIM_FIFOCTRL_REG ] = 0x4C ,
349+ [DSIM_PLLCTRL_REG ] = 0x94 ,
350+ [DSIM_PHYCTRL_REG ] = 0xA4 ,
351+ [DSIM_PHYTIMING_REG ] = 0xB4 ,
352+ [DSIM_PHYTIMING1_REG ] = 0xB8 ,
353+ [DSIM_PHYTIMING2_REG ] = 0xBC ,
354+ };
355+
323356enum reg_value_idx {
324357 RESET_TYPE ,
325358 PLL_TIMER ,
@@ -392,6 +425,24 @@ static const unsigned int exynos5433_reg_values[] = {
392425 [PHYTIMING_HS_TRAIL ] = DSIM_PHYTIMING2_HS_TRAIL (0x0c ),
393426};
394427
428+ static const unsigned int exynos7870_reg_values [] = {
429+ [RESET_TYPE ] = DSIM_SWRST ,
430+ [PLL_TIMER ] = 80000 ,
431+ [STOP_STATE_CNT ] = 0xa ,
432+ [PHYCTRL_ULPS_EXIT ] = DSIM_PHYCTRL_ULPS_EXIT (0x177 ),
433+ [PHYCTRL_VREG_LP ] = 0 ,
434+ [PHYCTRL_SLEW_UP ] = 0 ,
435+ [PHYTIMING_LPX ] = DSIM_PHYTIMING_LPX (0x07 ),
436+ [PHYTIMING_HS_EXIT ] = DSIM_PHYTIMING_HS_EXIT (0x0c ),
437+ [PHYTIMING_CLK_PREPARE ] = DSIM_PHYTIMING1_CLK_PREPARE (0x08 ),
438+ [PHYTIMING_CLK_ZERO ] = DSIM_PHYTIMING1_CLK_ZERO (0x2b ),
439+ [PHYTIMING_CLK_POST ] = DSIM_PHYTIMING1_CLK_POST (0x0d ),
440+ [PHYTIMING_CLK_TRAIL ] = DSIM_PHYTIMING1_CLK_TRAIL (0x09 ),
441+ [PHYTIMING_HS_PREPARE ] = DSIM_PHYTIMING2_HS_PREPARE (0x09 ),
442+ [PHYTIMING_HS_ZERO ] = DSIM_PHYTIMING2_HS_ZERO (0x0f ),
443+ [PHYTIMING_HS_TRAIL ] = DSIM_PHYTIMING2_HS_TRAIL (0x0c ),
444+ };
445+
395446static const unsigned int imx8mm_dsim_reg_values [] = {
396447 [RESET_TYPE ] = DSIM_SWRST ,
397448 [PLL_TIMER ] = 500 ,
@@ -563,6 +614,36 @@ static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = {
563614 .min_freq = 500 ,
564615};
565616
617+ static const struct samsung_dsim_driver_data exynos7870_dsi_driver_data = {
618+ .reg_ofs = exynos7870_reg_ofs ,
619+ .plltmr_reg = 0xa0 ,
620+ .has_clklane_stop = 1 ,
621+ .has_sfrctrl = 1 ,
622+ .clk_data = exynos7870_clk_bulk_data ,
623+ .num_clks = ARRAY_SIZE (exynos7870_clk_bulk_data ),
624+ .max_freq = 1500 ,
625+ .wait_for_hdr_fifo = 0 ,
626+ .wait_for_reset = 1 ,
627+ .num_bits_resol = 12 ,
628+ .video_mode_bit = 18 ,
629+ .pll_stable_bit = 24 ,
630+ .esc_clken_bit = 16 ,
631+ .byte_clken_bit = 17 ,
632+ .tx_req_hsclk_bit = 20 ,
633+ .lane_esc_clk_bit = 8 ,
634+ .lane_esc_data_offset = 9 ,
635+ .pll_p_offset = 13 ,
636+ .pll_m_offset = 3 ,
637+ .pll_s_offset = 0 ,
638+ .main_vsa_offset = 16 ,
639+ .reg_values = exynos7870_reg_values ,
640+ .pll_fin_min = 6 ,
641+ .pll_fin_max = 12 ,
642+ .m_min = 41 ,
643+ .m_max = 125 ,
644+ .min_freq = 500 ,
645+ };
646+
566647static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = {
567648 .reg_ofs = exynos5433_reg_ofs ,
568649 .plltmr_reg = 0xa0 ,
@@ -604,6 +685,7 @@ samsung_dsim_types[DSIM_TYPE_COUNT] = {
604685 [DSIM_TYPE_EXYNOS5410 ] = & exynos5_dsi_driver_data ,
605686 [DSIM_TYPE_EXYNOS5422 ] = & exynos5422_dsi_driver_data ,
606687 [DSIM_TYPE_EXYNOS5433 ] = & exynos5433_dsi_driver_data ,
688+ [DSIM_TYPE_EXYNOS7870 ] = & exynos7870_dsi_driver_data ,
607689 [DSIM_TYPE_IMX8MM ] = & imx8mm_dsi_driver_data ,
608690 [DSIM_TYPE_IMX8MP ] = & imx8mm_dsi_driver_data ,
609691};
0 commit comments