@@ -14,7 +14,7 @@ use crate::falcon::{
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use crate :: gpu:: { Architecture , Chipset } ;
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use kernel:: prelude:: * ;
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- /* PMC */
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+ // PMC
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register ! ( NV_PMC_BOOT_0 @ 0x00000000 , "Basic revision information about the GPU" {
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3 : 0 minor_revision as u8 , "Minor revision of the chip" ;
@@ -42,14 +42,14 @@ impl NV_PMC_BOOT_0 {
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}
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}
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- /* PBUS */
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+ // PBUS
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// TODO[REGA]: this is an array of registers.
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register ! ( NV_PBUS_SW_SCRATCH_0E @0x00001438 {
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31 : 16 frts_err_code as u16 ;
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} ) ;
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- /* PFB */
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+ // PFB
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// The following two registers together hold the physical system memory address that is used by the
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// GPU to perform sysmembar operations (see `fb::SysmemFlush`).
@@ -160,7 +160,7 @@ impl NV_USABLE_FB_SIZE_IN_MB {
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}
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}
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- /* PDISP */
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+ // PDISP
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register ! ( NV_PDISP_VGA_WORKSPACE_BASE @ 0x00625f04 {
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3 : 3 status_valid as bool , "Set if the `addr` field is valid" ;
@@ -178,7 +178,7 @@ impl NV_PDISP_VGA_WORKSPACE_BASE {
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}
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}
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- /* FUSE */
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+ // FUSE
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register ! ( NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION @ 0x00824100 {
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15 : 0 data as u16 ;
@@ -192,7 +192,7 @@ register!(NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION @ 0x008241c0 {
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15 : 0 data as u16 ;
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} ) ;
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- /* PFALCON */
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+ // PFALCON
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register ! ( NV_PFALCON_FALCON_IRQSCLR @ +0x00000004 {
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4 : 4 halt as bool ;
@@ -312,7 +312,7 @@ register!(NV_PFALCON2_FALCON_BROM_PARAADDR @ +0x00001210 {
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31 : 0 value as u32 ;
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} ) ;
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- /* PRISCV */
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+ // PRISCV
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register ! ( NV_PRISCV_RISCV_BCR_CTRL @ +0x00001668 {
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0 : 0 valid as bool ;
@@ -324,15 +324,15 @@ register!(NV_PRISCV_RISCV_BCR_CTRL @ +0x00001668 {
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// only be used in HAL modules.
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pub ( crate ) mod gm107 {
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- /* FUSE */
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+ // FUSE
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register ! ( NV_FUSE_STATUS_OPT_DISPLAY @ 0x00021c04 {
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0 : 0 display_disabled as bool ;
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} ) ;
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}
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pub ( crate ) mod ga100 {
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- /* FUSE */
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+ // FUSE
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register ! ( NV_FUSE_STATUS_OPT_DISPLAY @ 0x00820c04 {
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0 : 0 display_disabled as bool ;
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