drm/ast: Gen7: Switch default registers to gen4+ state

Change the default register settings for Gen7 to mach Gen4 and
later. Gen7 currently uses the settings for Gen1, which is most
likely incorrect.

Using Gen4+ settings enables E2M linear-access modes in VGACRA2.
It appears to be related to the chip's PCIE2MBOX feature, which
is unused.

Signed-off-by: Thomas Zimmermann <[email protected]>
Reviewed-by: Jocelyn Falempe <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

Author: tdz

drivers/gpu/drm/ast/ast_2600.c

@@ -33,40 +33,9 @@
  * POST
  */
 
-void ast_2600_set_def_ext_reg(struct ast_device *ast)
-{
-	static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
-	u8 i, index, reg;
-	const u8 *ext_reg_info;
-
-	/* reset scratch */
-	for (i = 0x81; i <= 0x9f; i++)
-		ast_set_index_reg(ast, AST_IO_VGACRI, i, 0x00);
-
-	ext_reg_info = extreginfo;
-	index = 0xa0;
-	while (*ext_reg_info != 0xff) {
-		ast_set_index_reg_mask(ast, AST_IO_VGACRI, index, 0x00, *ext_reg_info);
-		index++;
-		ext_reg_info++;
-	}
-
-	/* disable standard IO/MEM decode if secondary */
-	/* ast_set_index_reg-mask(ast, AST_IO_VGACRI, 0xa1, 0xff, 0x3); */
-
-	/* Set Ext. Default */
-	ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x8c, 0x00, 0x01);
-	ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x00, 0x00);
-
-	/* Enable RAMDAC for A1 */
-	reg = 0x04;
-	reg |= 0x20;
-	ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xff, reg);
-}
-
 int ast_2600_post(struct ast_device *ast)
 {
-	ast_2600_set_def_ext_reg(ast);
+	ast_2300_set_def_ext_reg(ast);
 
 	if (ast->tx_chip == AST_TX_ASTDP)
 		return ast_dp_launch(ast);

drivers/gpu/drm/ast/ast_post.h

@@ -47,7 +47,4 @@ void ast_2000_set_def_ext_reg(struct ast_device *ast);
 /* ast_2300.c */
 void ast_2300_set_def_ext_reg(struct ast_device *ast);
 
-/* ast_2600.c */
-void ast_2600_set_def_ext_reg(struct ast_device *ast);
-
 #endif