|
40 | 40 | #define VSC73XX_BLOCK_ARBITER 0x5 /* Only subblock 0 */
|
41 | 41 | #define VSC73XX_BLOCK_SYSTEM 0x7 /* Only subblock 0 */
|
42 | 42 |
|
| 43 | +/* MII Block subblock */ |
| 44 | +#define VSC73XX_BLOCK_MII_INTERNAL 0x0 /* Internal MDIO subblock */ |
| 45 | + |
43 | 46 | #define CPU_PORT 6 /* CPU port */
|
44 | 47 |
|
45 | 48 | /* MAC Block registers */
|
|
224 | 227 | #define VSC73XX_MII_STAT 0x0
|
225 | 228 | #define VSC73XX_MII_CMD 0x1
|
226 | 229 | #define VSC73XX_MII_DATA 0x2
|
| 230 | +#define VSC73XX_MII_MPRES 0x3 |
| 231 | + |
| 232 | +#define VSC73XX_MII_MPRES_NOPREAMBLE BIT(6) |
| 233 | +#define VSC73XX_MII_MPRES_PRESCALEVAL GENMASK(5, 0) |
| 234 | +#define VSC73XX_MII_PRESCALEVAL_MIN 3 /* min allowed mdio clock prescaler */ |
227 | 235 |
|
228 | 236 | /* Arbiter block 5 registers */
|
229 | 237 | #define VSC73XX_ARBEMPTY 0x0c
|
@@ -748,7 +756,7 @@ static int vsc73xx_configure_rgmii_port_delay(struct dsa_switch *ds)
|
748 | 756 | static int vsc73xx_setup(struct dsa_switch *ds)
|
749 | 757 | {
|
750 | 758 | struct vsc73xx *vsc = ds->priv;
|
751 |
| - int i, ret; |
| 759 | + int i, ret, val; |
752 | 760 |
|
753 | 761 | dev_info(vsc->dev, "set up the switch\n");
|
754 | 762 |
|
@@ -821,6 +829,15 @@ static int vsc73xx_setup(struct dsa_switch *ds)
|
821 | 829 |
|
822 | 830 | mdelay(50);
|
823 | 831 |
|
| 832 | + /* Disable preamble and use maximum allowed clock for the internal |
| 833 | + * mdio bus, used for communication with internal PHYs only. |
| 834 | + */ |
| 835 | + val = VSC73XX_MII_MPRES_NOPREAMBLE | |
| 836 | + FIELD_PREP(VSC73XX_MII_MPRES_PRESCALEVAL, |
| 837 | + VSC73XX_MII_PRESCALEVAL_MIN); |
| 838 | + vsc73xx_write(vsc, VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL, |
| 839 | + VSC73XX_MII_MPRES, val); |
| 840 | + |
824 | 841 | /* Release reset from the internal PHYs */
|
825 | 842 | vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GLORESET,
|
826 | 843 | VSC73XX_GLORESET_PHY_RESET);
|
|
0 commit comments