Skip to content

Commit 8e87b3e

Browse files
Cosmin RatiuPaolo Abeni
authored andcommitted
net/mlx5e: Do not fail PSP init on missing caps
PSP support requires a set of cap bits to be set, otherwise an init error is logged. But logging an error when PSP cannot be initialized is too much, and not in line with other features. If a feature cannot be initialized because it is not supported, that's not an error. An error should only be printed when the feature cannot be initialized because of an actual error. Fixes: 89ee2d9 ("net/mlx5e: Support PSP offload functionality") Signed-off-by: Cosmin Ratiu <[email protected]> Signed-off-by: Tariq Toukan <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Paolo Abeni <[email protected]>
1 parent 22239eb commit 8e87b3e

File tree

1 file changed

+5
-5
lines changed
  • drivers/net/ethernet/mellanox/mlx5/core/en_accel

1 file changed

+5
-5
lines changed

drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -893,27 +893,27 @@ int mlx5e_psp_init(struct mlx5e_priv *priv)
893893

894894
if (!mlx5_is_psp_device(mdev)) {
895895
mlx5_core_dbg(mdev, "PSP offload not supported\n");
896-
return -EOPNOTSUPP;
896+
return 0;
897897
}
898898

899899
if (!MLX5_CAP_ETH(mdev, swp)) {
900900
mlx5_core_dbg(mdev, "SWP not supported\n");
901-
return -EOPNOTSUPP;
901+
return 0;
902902
}
903903

904904
if (!MLX5_CAP_ETH(mdev, swp_csum)) {
905905
mlx5_core_dbg(mdev, "SWP checksum not supported\n");
906-
return -EOPNOTSUPP;
906+
return 0;
907907
}
908908

909909
if (!MLX5_CAP_ETH(mdev, swp_csum_l4_partial)) {
910910
mlx5_core_dbg(mdev, "SWP L4 partial checksum not supported\n");
911-
return -EOPNOTSUPP;
911+
return 0;
912912
}
913913

914914
if (!MLX5_CAP_ETH(mdev, swp_lso)) {
915915
mlx5_core_dbg(mdev, "PSP LSO not supported\n");
916-
return -EOPNOTSUPP;
916+
return 0;
917917
}
918918

919919
psp = kzalloc(sizeof(*psp), GFP_KERNEL);

0 commit comments

Comments
 (0)