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dtatuleakuba-moo
dtatulea
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kuba-moo
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net/mlx5e: Create/destroy PCIe Congestion Event object
Add initial infrastructure to create and destroy the PCIe Congestion Event object if the object is supported. The verb for the object creation function is "set" instead of "create" because the function will accommodate the modify operation as well in a subsequent patch. The next patches will hook it up to the event handler and will add actual functionality. Signed-off-by: Dragos Tatulea <[email protected]> Signed-off-by: Tariq Toukan <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
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‎drivers/net/ethernet/mellanox/mlx5/core/Makefile

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@ mlx5_core-$(CONFIG_MLX5_CORE_EN) += en/rqt.o en/tir.o en/rss.o en/rx_res.o \
2929
en/reporter_tx.o en/reporter_rx.o en/params.o en/xsk/pool.o \
3030
en/xsk/setup.o en/xsk/rx.o en/xsk/tx.o en/devlink.o en/ptp.o \
3131
en/qos.o en/htb.o en/trap.o en/fs_tt_redirect.o en/selq.o \
32-
lib/crypto.o lib/sd.o
32+
lib/crypto.o lib/sd.o en/pcie_cong_event.o
3333

3434
#
3535
# Netdev extra

‎drivers/net/ethernet/mellanox/mlx5/core/en.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -920,6 +920,8 @@ struct mlx5e_priv {
920920
struct notifier_block events_nb;
921921
struct notifier_block blocking_events_nb;
922922

923+
struct mlx5e_pcie_cong_event *cong_event;
924+
923925
struct udp_tunnel_nic_info nic_info;
924926
#ifdef CONFIG_MLX5_CORE_EN_DCB
925927
struct mlx5e_dcbx dcbx;

‎drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c

Lines changed: 140 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,140 @@
1+
// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2+
// Copyright (c) 2025, NVIDIA CORPORATION & AFFILIATES.
3+
4+
#include "en.h"
5+
#include "pcie_cong_event.h"
6+
7+
struct mlx5e_pcie_cong_thresh {
8+
u16 inbound_high;
9+
u16 inbound_low;
10+
u16 outbound_high;
11+
u16 outbound_low;
12+
};
13+
14+
struct mlx5e_pcie_cong_event {
15+
u64 obj_id;
16+
17+
struct mlx5e_priv *priv;
18+
};
19+
20+
/* In units of 0.01 % */
21+
static const struct mlx5e_pcie_cong_thresh default_thresh_config = {
22+
.inbound_high = 9000,
23+
.inbound_low = 7500,
24+
.outbound_high = 9000,
25+
.outbound_low = 7500,
26+
};
27+
28+
static int
29+
mlx5_cmd_pcie_cong_event_set(struct mlx5_core_dev *dev,
30+
const struct mlx5e_pcie_cong_thresh *config,
31+
u64 *obj_id)
32+
{
33+
u32 in[MLX5_ST_SZ_DW(pcie_cong_event_cmd_in)] = {};
34+
u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
35+
void *cong_obj;
36+
void *hdr;
37+
int err;
38+
39+
hdr = MLX5_ADDR_OF(pcie_cong_event_cmd_in, in, hdr);
40+
cong_obj = MLX5_ADDR_OF(pcie_cong_event_cmd_in, in, cong_obj);
41+
42+
MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
43+
MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
44+
45+
MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
46+
MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT);
47+
48+
MLX5_SET(pcie_cong_event_obj, cong_obj, inbound_event_en, 1);
49+
MLX5_SET(pcie_cong_event_obj, cong_obj, outbound_event_en, 1);
50+
51+
MLX5_SET(pcie_cong_event_obj, cong_obj,
52+
inbound_cong_high_threshold, config->inbound_high);
53+
MLX5_SET(pcie_cong_event_obj, cong_obj,
54+
inbound_cong_low_threshold, config->inbound_low);
55+
56+
MLX5_SET(pcie_cong_event_obj, cong_obj,
57+
outbound_cong_high_threshold, config->outbound_high);
58+
MLX5_SET(pcie_cong_event_obj, cong_obj,
59+
outbound_cong_low_threshold, config->outbound_low);
60+
61+
err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
62+
if (err)
63+
return err;
64+
65+
*obj_id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
66+
67+
mlx5_core_dbg(dev, "PCIe congestion event (obj_id=%llu) created. Config: in: [%u, %u], out: [%u, %u]\n",
68+
*obj_id,
69+
config->inbound_high, config->inbound_low,
70+
config->outbound_high, config->outbound_low);
71+
72+
return 0;
73+
}
74+
75+
static int mlx5_cmd_pcie_cong_event_destroy(struct mlx5_core_dev *dev,
76+
u64 obj_id)
77+
{
78+
u32 in[MLX5_ST_SZ_DW(pcie_cong_event_cmd_in)] = {};
79+
u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
80+
void *hdr;
81+
82+
hdr = MLX5_ADDR_OF(pcie_cong_event_cmd_in, in, hdr);
83+
MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
84+
MLX5_CMD_OP_DESTROY_GENERAL_OBJECT);
85+
MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
86+
MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT);
87+
MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, obj_id);
88+
89+
return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
90+
}
91+
92+
int mlx5e_pcie_cong_event_init(struct mlx5e_priv *priv)
93+
{
94+
struct mlx5e_pcie_cong_event *cong_event;
95+
struct mlx5_core_dev *mdev = priv->mdev;
96+
int err;
97+
98+
if (!mlx5_pcie_cong_event_supported(mdev))
99+
return 0;
100+
101+
cong_event = kvzalloc_node(sizeof(*cong_event), GFP_KERNEL,
102+
mdev->priv.numa_node);
103+
if (!cong_event)
104+
return -ENOMEM;
105+
106+
cong_event->priv = priv;
107+
108+
err = mlx5_cmd_pcie_cong_event_set(mdev, &default_thresh_config,
109+
&cong_event->obj_id);
110+
if (err) {
111+
mlx5_core_warn(mdev, "Error creating a PCIe congestion event object\n");
112+
goto err_free;
113+
}
114+
115+
priv->cong_event = cong_event;
116+
117+
return 0;
118+
119+
err_free:
120+
kvfree(cong_event);
121+
122+
return err;
123+
}
124+
125+
void mlx5e_pcie_cong_event_cleanup(struct mlx5e_priv *priv)
126+
{
127+
struct mlx5e_pcie_cong_event *cong_event = priv->cong_event;
128+
struct mlx5_core_dev *mdev = priv->mdev;
129+
130+
if (!cong_event)
131+
return;
132+
133+
priv->cong_event = NULL;
134+
135+
if (mlx5_cmd_pcie_cong_event_destroy(mdev, cong_event->obj_id))
136+
mlx5_core_warn(mdev, "Error destroying PCIe congestion event (obj_id=%llu)\n",
137+
cong_event->obj_id);
138+
139+
kvfree(cong_event);
140+
}

‎drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.h

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2+
/* Copyright (c) 2025, NVIDIA CORPORATION & AFFILIATES. */
3+
4+
#ifndef __MLX5_PCIE_CONG_EVENT_H__
5+
#define __MLX5_PCIE_CONG_EVENT_H__
6+
7+
int mlx5e_pcie_cong_event_init(struct mlx5e_priv *priv);
8+
void mlx5e_pcie_cong_event_cleanup(struct mlx5e_priv *priv);
9+
10+
#endif /* __MLX5_PCIE_CONG_EVENT_H__ */

‎drivers/net/ethernet/mellanox/mlx5/core/en_main.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -76,6 +76,7 @@
7676
#include "en/trap.h"
7777
#include "lib/devcom.h"
7878
#include "lib/sd.h"
79+
#include "en/pcie_cong_event.h"
7980

8081
static bool mlx5e_hw_gro_supported(struct mlx5_core_dev *mdev)
8182
{
@@ -5989,6 +5990,7 @@ static void mlx5e_nic_enable(struct mlx5e_priv *priv)
59895990
if (mlx5e_monitor_counter_supported(priv))
59905991
mlx5e_monitor_counter_init(priv);
59915992

5993+
mlx5e_pcie_cong_event_init(priv);
59925994
mlx5e_hv_vhca_stats_create(priv);
59935995
if (netdev->reg_state != NETREG_REGISTERED)
59945996
return;
@@ -6028,6 +6030,7 @@ static void mlx5e_nic_disable(struct mlx5e_priv *priv)
60286030

60296031
mlx5e_nic_set_rx_mode(priv);
60306032

6033+
mlx5e_pcie_cong_event_cleanup(priv);
60316034
mlx5e_hv_vhca_stats_destroy(priv);
60326035
if (mlx5e_monitor_counter_supported(priv))
60336036
mlx5e_monitor_counter_cleanup(priv);

‎drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -495,4 +495,17 @@ static inline int mlx5_max_eq_cap_get(const struct mlx5_core_dev *dev)
495495

496496
return 1 << MLX5_CAP_GEN(dev, log_max_eq);
497497
}
498+
499+
static inline bool mlx5_pcie_cong_event_supported(struct mlx5_core_dev *dev)
500+
{
501+
u64 features = MLX5_CAP_GEN_2_64(dev, general_obj_types_127_64);
502+
503+
if (!(features & MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT))
504+
return false;
505+
506+
if (dev->sd)
507+
return false;
508+
509+
return true;
510+
}
498511
#endif /* __MLX5_CORE_H__ */

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