dt-bindings: clock: xilinx: Add reset GPIO for VCU

It is marked as optional as some of the ZynqMP designs are having vcu_reset
(reset pin of VCU IP) driven by proc_sys_reset, proc_sys_reset is another
PL IP driven by the PS pl_reset. So, here the VCU reset is not driven by
axi_gpio or PS GPIO so there will be no GPIO entry.

Signed-off-by: Rohit Visavalia <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

Author: rohitvisavalia

Documentation/devicetree/bindings/clock/xlnx,vcu.yaml

@@ -33,6 +33,9 @@ properties:
       - const: pll_ref
       - const: aclk
 
+  reset-gpios:
+    maxItems: 1
+
 required:
   - reg
   - clocks
@@ -49,6 +52,7 @@ examples:
         xlnx_vcu: vcu@a0040000 {
             compatible = "xlnx,vcu-logicoreip-1.0";
             reg = <0x0 0xa0040000 0x0 0x1000>;
+            reset-gpios = <&gpio 78 GPIO_ACTIVE_HIGH>;
             clocks = <&si570_1>, <&clkc 71>;
             clock-names = "pll_ref", "aclk";
         };