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quic-kdybcioRob Clark
authored andcommitted
drm/msm/a6xx: Resolve the meaning of rgb565_predicator
It's supposed to be on when the UBWC encoder version is >= 4.0. Drop the per-GPU assignments. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/660975/ Signed-off-by: Rob Clark <[email protected]>
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drivers/gpu/drm/msm/adreno/a6xx_gpu.c

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -611,7 +611,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
611611
if (IS_ERR(gpu->common_ubwc_cfg))
612612
return PTR_ERR(gpu->common_ubwc_cfg);
613613

614-
gpu->ubwc_config.rgb565_predicator = 0;
615614
gpu->ubwc_config.min_acc_len = 0;
616615
gpu->ubwc_config.ubwc_swizzle = 0x6;
617616
gpu->ubwc_config.macrotile_mode = 0;
@@ -638,7 +637,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
638637

639638
if (adreno_is_a623(gpu)) {
640639
gpu->ubwc_config.highest_bank_bit = 16;
641-
gpu->ubwc_config.rgb565_predicator = 1;
642640
gpu->ubwc_config.macrotile_mode = 1;
643641
}
644642

@@ -652,13 +650,11 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
652650
adreno_is_a740_family(gpu)) {
653651
/* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
654652
gpu->ubwc_config.highest_bank_bit = 16;
655-
gpu->ubwc_config.rgb565_predicator = 1;
656653
gpu->ubwc_config.macrotile_mode = 1;
657654
}
658655

659656
if (adreno_is_a663(gpu)) {
660657
gpu->ubwc_config.highest_bank_bit = 13;
661-
gpu->ubwc_config.rgb565_predicator = 1;
662658
gpu->ubwc_config.macrotile_mode = 1;
663659
gpu->ubwc_config.ubwc_swizzle = 0x4;
664660
}
@@ -687,6 +683,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
687683
*/
688684
BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13);
689685
u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13;
686+
bool rgb565_predicator = cfg->ubwc_enc_version >= UBWC_4_0;
690687
u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & BIT(1));
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bool ubwc_mode = qcom_ubwc_get_ubwc_mode(cfg);
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bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0;
@@ -699,7 +696,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
699696

700697
gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
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level2_swizzling_dis << 12 |
702-
adreno_gpu->ubwc_config.rgb565_predicator << 11 |
699+
rgb565_predicator << 11 |
703700
hbb_hi << 10 | amsbc << 4 |
704701
adreno_gpu->ubwc_config.min_acc_len << 3 |
705702
hbb_lo << 1 | ubwc_mode);

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