@@ -611,7 +611,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
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if (IS_ERR (gpu -> common_ubwc_cfg ))
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return PTR_ERR (gpu -> common_ubwc_cfg );
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- gpu -> ubwc_config .rgb565_predicator = 0 ;
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gpu -> ubwc_config .min_acc_len = 0 ;
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gpu -> ubwc_config .ubwc_swizzle = 0x6 ;
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gpu -> ubwc_config .macrotile_mode = 0 ;
@@ -638,7 +637,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
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if (adreno_is_a623 (gpu )) {
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gpu -> ubwc_config .highest_bank_bit = 16 ;
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- gpu -> ubwc_config .rgb565_predicator = 1 ;
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gpu -> ubwc_config .macrotile_mode = 1 ;
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}
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@@ -652,13 +650,11 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
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adreno_is_a740_family (gpu )) {
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/* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
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gpu -> ubwc_config .highest_bank_bit = 16 ;
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- gpu -> ubwc_config .rgb565_predicator = 1 ;
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gpu -> ubwc_config .macrotile_mode = 1 ;
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}
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if (adreno_is_a663 (gpu )) {
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gpu -> ubwc_config .highest_bank_bit = 13 ;
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- gpu -> ubwc_config .rgb565_predicator = 1 ;
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gpu -> ubwc_config .macrotile_mode = 1 ;
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gpu -> ubwc_config .ubwc_swizzle = 0x4 ;
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}
@@ -687,6 +683,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
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*/
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BUG_ON (adreno_gpu -> ubwc_config .highest_bank_bit < 13 );
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u32 hbb = adreno_gpu -> ubwc_config .highest_bank_bit - 13 ;
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+ bool rgb565_predicator = cfg -> ubwc_enc_version >= UBWC_4_0 ;
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u32 level2_swizzling_dis = !(cfg -> ubwc_swizzle & BIT (1 ));
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bool ubwc_mode = qcom_ubwc_get_ubwc_mode (cfg );
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bool amsbc = cfg -> ubwc_enc_version >= UBWC_3_0 ;
@@ -699,7 +696,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
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gpu_write (gpu , REG_A6XX_RB_NC_MODE_CNTL ,
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level2_swizzling_dis << 12 |
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- adreno_gpu -> ubwc_config . rgb565_predicator << 11 |
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+ rgb565_predicator << 11 |
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hbb_hi << 10 | amsbc << 4 |
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adreno_gpu -> ubwc_config .min_acc_len << 3 |
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hbb_lo << 1 | ubwc_mode );
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