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Wesley Chengvinodkoul
Wesley Cheng
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vinodkoul
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phy: qcom: qmp-combo: Add new PHY sequences for SM8750
Add new register offsets and PHY values for SM8750. Some of the previous definitions can be leveraged from older PHY versions as offsets within registers have not changed. This also adds the required PHY sequence that is recommended after running hardware characterization. Signed-off-by: Wesley Cheng <[email protected]> Signed-off-by: Melody Olvera <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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‎drivers/phy/qualcomm/phy-qcom-qmp-combo.c

Lines changed: 221 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@
3232
#include "phy-qcom-qmp-pcs-usb-v4.h"
3333
#include "phy-qcom-qmp-pcs-usb-v5.h"
3434
#include "phy-qcom-qmp-pcs-usb-v6.h"
35+
#include "phy-qcom-qmp-pcs-usb-v8.h"
3536

3637
#include "phy-qcom-qmp-dp-com-v3.h"
3738

@@ -212,6 +213,28 @@ static const unsigned int qmp_v6_n4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
212213
[QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_N4_TX_TRANSCEIVER_BIAS_EN,
213214
};
214215

216+
static const unsigned int qmp_v8_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
217+
[QPHY_SW_RESET] = QPHY_V8_PCS_SW_RESET,
218+
[QPHY_START_CTRL] = QPHY_V8_PCS_START_CONTROL,
219+
[QPHY_PCS_STATUS] = QPHY_V8_PCS_PCS_STATUS1,
220+
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V8_PCS_POWER_DOWN_CONTROL,
221+
222+
/* In PCS_USB */
223+
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL,
224+
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_CLEAR,
225+
226+
[QPHY_COM_RESETSM_CNTRL] = QSERDES_V8_COM_RESETSM_CNTRL,
227+
[QPHY_COM_C_READY_STATUS] = QSERDES_V8_COM_C_READY_STATUS,
228+
[QPHY_COM_CMN_STATUS] = QSERDES_V8_COM_CMN_STATUS,
229+
[QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN,
230+
231+
[QPHY_TX_TX_POL_INV] = QSERDES_V8_TX_TX_POL_INV,
232+
[QPHY_TX_TX_DRV_LVL] = QSERDES_V8_TX_TX_DRV_LVL,
233+
[QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V8_TX_TX_EMP_POST1_LVL,
234+
[QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V8_TX_HIGHZ_DRVR_EN,
235+
[QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V8_TX_TRANSCEIVER_BIAS_EN,
236+
};
237+
215238
static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
216239
QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
217240
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
@@ -1471,6 +1494,139 @@ static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_tbl[] = {
14711494
QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_EQ_CONFIG5, 0x10),
14721495
};
14731496

1497+
static const struct qmp_phy_init_tbl sm8750_usb3_serdes_tbl[] = {
1498+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE1_MODE1, 0xc0),
1499+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE2_MODE1, 0x01),
1500+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE1, 0x02),
1501+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE1, 0x16),
1502+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE1, 0x36),
1503+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_CORECLK_DIV_MODE1, 0x04),
1504+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE1, 0x16),
1505+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE1, 0x41),
1506+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE1, 0x41),
1507+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MSB_MODE1, 0x00),
1508+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START1_MODE1, 0x55),
1509+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START2_MODE1, 0x75),
1510+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START3_MODE1, 0x01),
1511+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_HSCLK_SEL_1, 0x01),
1512+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE1_MODE1, 0x25),
1513+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE2_MODE1, 0x02),
1514+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c),
1515+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f),
1516+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c),
1517+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f),
1518+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0, 0xc0),
1519+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1520+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE0, 0x02),
1521+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE0, 0x16),
1522+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE0, 0x36),
1523+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE0, 0x08),
1524+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE0, 0x1a),
1525+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE0, 0x41),
1526+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MSB_MODE0, 0x00),
1527+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START1_MODE0, 0x55),
1528+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START2_MODE0, 0x75),
1529+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START3_MODE0, 0x01),
1530+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE1_MODE0, 0x25),
1531+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE2_MODE0, 0x02),
1532+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_BG_TIMER, 0x0a),
1533+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_EN_CENTER, 0x01),
1534+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_PER1, 0x62),
1535+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_PER2, 0x02),
1536+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_BUF_ENABLE, 0x0c),
1537+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_EN_SEL, 0x1a),
1538+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP_CFG, 0x14),
1539+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE_MAP, 0x04),
1540+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_CORE_CLK_EN, 0x20),
1541+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_CONFIG_1, 0x16),
1542+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),
1543+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4a),
1544+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_3, 0x36),
1545+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_ADDITIONAL_MISC, 0x0c),
1546+
};
1547+
1548+
static const struct qmp_phy_init_tbl sm8750_usb3_tx_tbl[] = {
1549+
QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_TX, 0x00),
1550+
QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_RX, 0x00),
1551+
QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
1552+
QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
1553+
QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_1, 0xf5),
1554+
QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_3, 0x11),
1555+
QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_4, 0x31),
1556+
QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_5, 0x5f),
1557+
QMP_PHY_INIT_CFG(QSERDES_V8_TX_RCV_DETECT_LVL_2, 0x12),
1558+
QMP_PHY_INIT_CFG_LANE(QSERDES_V8_TX_PI_QEC_CTRL, 0x21, 1),
1559+
QMP_PHY_INIT_CFG_LANE(QSERDES_V8_TX_PI_QEC_CTRL, 0x05, 2),
1560+
};
1561+
1562+
static const struct qmp_phy_init_tbl sm8750_usb3_rx_tbl[] = {
1563+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FO_GAIN, 0x0a),
1564+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SO_GAIN, 0x06),
1565+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1566+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1567+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1568+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1569+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_PI_CONTROLS, 0x99),
1570+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_THRESH1, 0x08),
1571+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_THRESH2, 0x08),
1572+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_GAIN1, 0x00),
1573+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_GAIN2, 0x0a),
1574+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_AUX_DATA_TCOARSE_TFINE, 0x20),
1575+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_VGA_CAL_CNTRL1, 0x54),
1576+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_VGA_CAL_CNTRL2, 0x0f),
1577+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_GM_CAL, 0x13),
1578+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
1579+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1580+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1581+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_IDAC_TSETTLE_LOW, 0x07),
1582+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1583+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
1584+
1585+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_ENABLES, 0x0c),
1586+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CNTRL, 0x04),
1587+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1588+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_LOW, 0x3f),
1589+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH, 0xbf),
1590+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH2, 0xff),
1591+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH3, 0xdf),
1592+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH4, 0xed),
1593+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_LOW, 0x19),
1594+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH, 0x09),
1595+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH2, 0x91),
1596+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH3, 0xb7),
1597+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH4, 0xaa),
1598+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_DFE_EN_TIMER, 0x04),
1599+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1600+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_DCC_CTRL1, 0x0c),
1601+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_VTH_CODE, 0x10),
1602+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CAL_CTRL1, 0x14),
1603+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CAL_TRIM, 0x08),
1604+
};
1605+
1606+
static const struct qmp_phy_init_tbl sm8750_usb3_pcs_tbl[] = {
1607+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG1, 0xc4),
1608+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG2, 0x89),
1609+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG3, 0x20),
1610+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG6, 0x13),
1611+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_REFGEN_REQ_CONFIG1, 0x21),
1612+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_RX_SIGDET_LVL, 0x55),
1613+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1614+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1615+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_CDR_RESET_TIME, 0x0a),
1616+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1617+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1618+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_PCS_TX_RX_CONFIG, 0x0c),
1619+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_EQ_CONFIG1, 0x4b),
1620+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_EQ_CONFIG5, 0x10),
1621+
};
1622+
1623+
static const struct qmp_phy_init_tbl sm8750_usb3_pcs_usb_tbl[] = {
1624+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1625+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RXEQTRAINING_DFE_TIME_S2, 0x07),
1626+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_L, 0x40),
1627+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_H, 0x00),
1628+
};
1629+
14741630
static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_usb_tbl[] = {
14751631
QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
14761632
QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
@@ -1781,6 +1937,22 @@ static const struct qmp_combo_offsets qmp_combo_offsets_v5 = {
17811937
.dp_dp_phy = 0x2200,
17821938
};
17831939

1940+
static const struct qmp_combo_offsets qmp_combo_offsets_v8 = {
1941+
.com = 0x0000,
1942+
.txa = 0x1400,
1943+
.rxa = 0x1600,
1944+
.txb = 0x1800,
1945+
.rxb = 0x1a00,
1946+
.usb3_serdes = 0x1000,
1947+
.usb3_pcs_misc = 0x1c00,
1948+
.usb3_pcs = 0x1e00,
1949+
.usb3_pcs_usb = 0x2100,
1950+
.dp_serdes = 0x3000,
1951+
.dp_txa = 0x3400,
1952+
.dp_txb = 0x3800,
1953+
.dp_dp_phy = 0x3c00,
1954+
};
1955+
17841956
static const struct qmp_phy_cfg sar2130p_usb3dpphy_cfg = {
17851957
.offsets = &qmp_combo_offsets_v3,
17861958

@@ -2280,6 +2452,51 @@ static const struct qmp_phy_cfg sm8650_usb3dpphy_cfg = {
22802452
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
22812453
};
22822454

2455+
static const struct qmp_phy_cfg sm8750_usb3dpphy_cfg = {
2456+
.offsets = &qmp_combo_offsets_v8,
2457+
2458+
.serdes_tbl = sm8750_usb3_serdes_tbl,
2459+
.serdes_tbl_num = ARRAY_SIZE(sm8750_usb3_serdes_tbl),
2460+
.tx_tbl = sm8750_usb3_tx_tbl,
2461+
.tx_tbl_num = ARRAY_SIZE(sm8750_usb3_tx_tbl),
2462+
.rx_tbl = sm8750_usb3_rx_tbl,
2463+
.rx_tbl_num = ARRAY_SIZE(sm8750_usb3_rx_tbl),
2464+
.pcs_tbl = sm8750_usb3_pcs_tbl,
2465+
.pcs_tbl_num = ARRAY_SIZE(sm8750_usb3_pcs_tbl),
2466+
.pcs_usb_tbl = sm8750_usb3_pcs_usb_tbl,
2467+
.pcs_usb_tbl_num = ARRAY_SIZE(sm8750_usb3_pcs_usb_tbl),
2468+
2469+
.dp_serdes_tbl = qmp_v6_dp_serdes_tbl,
2470+
.dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl),
2471+
.dp_tx_tbl = qmp_v6_dp_tx_tbl,
2472+
.dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl),
2473+
2474+
.serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr,
2475+
.serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr),
2476+
.serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr,
2477+
.serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr),
2478+
.serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2,
2479+
.serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2),
2480+
.serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3,
2481+
.serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3),
2482+
2483+
.swing_hbr_rbr = &qmp_dp_v6_voltage_swing_hbr_rbr,
2484+
.pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr,
2485+
.swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
2486+
.pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
2487+
2488+
.dp_aux_init = qmp_v4_dp_aux_init,
2489+
.configure_dp_tx = qmp_v4_configure_dp_tx,
2490+
.configure_dp_phy = qmp_v4_configure_dp_phy,
2491+
.calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
2492+
2493+
.regs = qmp_v8_usb3phy_regs_layout,
2494+
.reset_list = msm8996_usb3phy_reset_l,
2495+
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2496+
.vreg_list = qmp_phy_vreg_l,
2497+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2498+
};
2499+
22832500
static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp)
22842501
{
22852502
const struct qmp_phy_cfg *cfg = qmp->cfg;
@@ -3915,6 +4132,10 @@ static const struct of_device_id qmp_combo_of_match_table[] = {
39154132
.compatible = "qcom,sm8650-qmp-usb3-dp-phy",
39164133
.data = &sm8650_usb3dpphy_cfg,
39174134
},
4135+
{
4136+
.compatible = "qcom,sm8750-qmp-usb3-dp-phy",
4137+
.data = &sm8750_usb3dpphy_cfg,
4138+
},
39184139
{
39194140
.compatible = "qcom,x1e80100-qmp-usb3-dp-phy",
39204141
.data = &x1e80100_usb3dpphy_cfg,

‎drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v8.h

Lines changed: 38 additions & 0 deletions
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1+
/* SPDX-License-Identifier: GPL-2.0 */
2+
/*
3+
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
4+
*/
5+
6+
#ifndef QCOM_PHY_QMP_PCS_USB_V8_H_
7+
#define QCOM_PHY_QMP_PCS_USB_V8_H_
8+
9+
#define QPHY_V8_PCS_USB_POWER_STATE_CONFIG1 0x00
10+
#define QPHY_V8_PCS_USB_AUTONOMOUS_MODE_STATUS 0x04
11+
#define QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL 0x08
12+
#define QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL2 0x0c
13+
#define QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x10
14+
#define QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_CLEAR 0x14
15+
#define QPHY_V8_PCS_USB_LFPS_DET_HIGH_COUNT_VAL 0x18
16+
#define QPHY_V8_PCS_USB_LFPS_TX_ECSTART 0x1c
17+
#define QPHY_V8_PCS_USB_LFPS_PER_TIMER_VAL 0x20
18+
#define QPHY_V8_PCS_USB_LFPS_TX_END_CNT_U3_START 0x24
19+
#define QPHY_V8_PCS_USB_LFPS_CONFIG1 0x28
20+
#define QPHY_V8_PCS_USB_RXEQTRAINING_LOCK_TIME 0x2c
21+
#define QPHY_V8_PCS_USB_RXEQTRAINING_WAIT_TIME 0x30
22+
#define QPHY_V8_PCS_USB_RXEQTRAINING_CTLE_TIME 0x34
23+
#define QPHY_V8_PCS_USB_RXEQTRAINING_WAIT_TIME_S2 0x38
24+
#define QPHY_V8_PCS_USB_RXEQTRAINING_DFE_TIME_S2 0x3c
25+
#define QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_L 0x40
26+
#define QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_H 0x44
27+
#define QPHY_V8_PCS_USB_ARCVR_DTCT_EN_PERIOD 0x48
28+
#define QPHY_V8_PCS_USB_ARCVR_DTCT_CM_DLY 0x4c
29+
#define QPHY_V8_PCS_USB_TXONESZEROS_RUN_LENGTH 0x50
30+
#define QPHY_V8_PCS_USB_ALFPS_DEGLITCH_VAL 0x54
31+
#define QPHY_V8_PCS_USB_SIGDET_STARTUP_TIMER_VAL 0x58
32+
#define QPHY_V8_PCS_USB_TEST_CONTROL 0x5c
33+
#define QPHY_V8_PCS_USB_RXTERMINATION_DLY_SEL 0x60
34+
#define QPHY_V8_PCS_USB_POWER_STATE_CONFIG2 0x64
35+
#define QPHY_V8_PCS_USB_POWER_STATE_CONFIG3 0x68
36+
#define QPHY_V8_PCS_USB_POWER_STATE_CONFIG4 0x6c
37+
38+
#endif

‎drivers/phy/qualcomm/phy-qcom-qmp-pcs-v8.h

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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1+
/* SPDX-License-Identifier: GPL-2.0 */
2+
/*
3+
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
4+
*/
5+
6+
#ifndef QCOM_PHY_QMP_PCS_V8_H_
7+
#define QCOM_PHY_QMP_PCS_V8_H_
8+
9+
/* Only for QMP V8 PHY - USB/PCIe PCS registers */
10+
#define QPHY_V8_PCS_SW_RESET 0x000
11+
#define QPHY_V8_PCS_PCS_STATUS1 0x014
12+
#define QPHY_V8_PCS_POWER_DOWN_CONTROL 0x040
13+
#define QPHY_V8_PCS_START_CONTROL 0x044
14+
#define QPHY_V8_PCS_POWER_STATE_CONFIG1 0x090
15+
#define QPHY_V8_PCS_LOCK_DETECT_CONFIG1 0x0c4
16+
#define QPHY_V8_PCS_LOCK_DETECT_CONFIG2 0x0c8
17+
#define QPHY_V8_PCS_LOCK_DETECT_CONFIG3 0x0cc
18+
#define QPHY_V8_PCS_LOCK_DETECT_CONFIG6 0x0d8
19+
#define QPHY_V8_PCS_REFGEN_REQ_CONFIG1 0x0dc
20+
#define QPHY_V8_PCS_RX_SIGDET_LVL 0x188
21+
#define QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
22+
#define QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
23+
#define QPHY_V8_PCS_RATE_SLEW_CNTRL1 0x198
24+
#define QPHY_V8_PCS_CDR_RESET_TIME 0x1b0
25+
#define QPHY_V8_PCS_ALIGN_DETECT_CONFIG1 0x1c0
26+
#define QPHY_V8_PCS_ALIGN_DETECT_CONFIG2 0x1c4
27+
#define QPHY_V8_PCS_PCS_TX_RX_CONFIG 0x1d0
28+
#define QPHY_V8_PCS_EQ_CONFIG1 0x1dc
29+
#define QPHY_V8_PCS_EQ_CONFIG2 0x1e0
30+
#define QPHY_V8_PCS_EQ_CONFIG5 0x1ec
31+
32+
#endif

‎drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h

Lines changed: 64 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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1+
/* SPDX-License-Identifier: GPL-2.0 */
2+
/*
3+
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
4+
*/
5+
6+
#ifndef QCOM_PHY_QMP_QSERDES_COM_V8_H_
7+
#define QCOM_PHY_QMP_QSERDES_COM_V8_H_
8+
9+
/* Only for QMP V8 PHY - QSERDES COM registers */
10+
#define QSERDES_V8_COM_SSC_STEP_SIZE1_MODE1 0x000
11+
#define QSERDES_V8_COM_SSC_STEP_SIZE2_MODE1 0x004
12+
#define QSERDES_V8_COM_SSC_STEP_SIZE3_MODE1 0x008
13+
#define QSERDES_V8_COM_CP_CTRL_MODE1 0x010
14+
#define QSERDES_V8_COM_PLL_RCTRL_MODE1 0x014
15+
#define QSERDES_V8_COM_PLL_CCTRL_MODE1 0x018
16+
#define QSERDES_V8_COM_CORECLK_DIV_MODE1 0x01c
17+
#define QSERDES_V8_COM_LOCK_CMP1_MODE1 0x020
18+
#define QSERDES_V8_COM_LOCK_CMP2_MODE1 0x024
19+
#define QSERDES_V8_COM_DEC_START_MODE1 0x028
20+
#define QSERDES_V8_COM_DEC_START_MSB_MODE1 0x02c
21+
#define QSERDES_V8_COM_DIV_FRAC_START1_MODE1 0x030
22+
#define QSERDES_V8_COM_DIV_FRAC_START2_MODE1 0x034
23+
#define QSERDES_V8_COM_DIV_FRAC_START3_MODE1 0x038
24+
#define QSERDES_V8_COM_HSCLK_SEL_1 0x03c
25+
#define QSERDES_V8_COM_VCO_TUNE1_MODE1 0x048
26+
#define QSERDES_V8_COM_VCO_TUNE2_MODE1 0x04c
27+
#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x050
28+
#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x054
29+
#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x058
30+
#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x05c
31+
#define QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0 0x060
32+
#define QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0 0x064
33+
#define QSERDES_V8_COM_CP_CTRL_MODE0 0x070
34+
#define QSERDES_V8_COM_PLL_RCTRL_MODE0 0x074
35+
#define QSERDES_V8_COM_PLL_CCTRL_MODE0 0x078
36+
#define QSERDES_V8_COM_LOCK_CMP1_MODE0 0x080
37+
#define QSERDES_V8_COM_LOCK_CMP2_MODE0 0x084
38+
#define QSERDES_V8_COM_DEC_START_MODE0 0x088
39+
#define QSERDES_V8_COM_DEC_START_MSB_MODE0 0x08c
40+
#define QSERDES_V8_COM_DIV_FRAC_START1_MODE0 0x090
41+
#define QSERDES_V8_COM_DIV_FRAC_START2_MODE0 0x094
42+
#define QSERDES_V8_COM_DIV_FRAC_START3_MODE0 0x098
43+
#define QSERDES_V8_COM_VCO_TUNE1_MODE0 0x0a8
44+
#define QSERDES_V8_COM_VCO_TUNE2_MODE0 0x0ac
45+
#define QSERDES_V8_COM_BG_TIMER 0x0bc
46+
#define QSERDES_V8_COM_SSC_EN_CENTER 0x0c0
47+
#define QSERDES_V8_COM_SSC_PER1 0x0cc
48+
#define QSERDES_V8_COM_SSC_PER2 0x0d0
49+
#define QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN 0x0dc
50+
#define QSERDES_V8_COM_SYSCLK_BUF_ENABLE 0x0e8
51+
#define QSERDES_V8_COM_SYSCLK_EN_SEL 0x110
52+
#define QSERDES_V8_COM_RESETSM_CNTRL 0x118
53+
#define QSERDES_V8_COM_LOCK_CMP_CFG 0x124
54+
#define QSERDES_V8_COM_VCO_TUNE_MAP 0x140
55+
#define QSERDES_V8_COM_CORE_CLK_EN 0x170
56+
#define QSERDES_V8_COM_CMN_CONFIG_1 0x174
57+
#define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_1 0x1a4
58+
#define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_2 0x1a8
59+
#define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_3 0x1ac
60+
#define QSERDES_V8_COM_ADDITIONAL_MISC 0x1b4
61+
#define QSERDES_V8_COM_CMN_STATUS 0x2c8
62+
#define QSERDES_V8_COM_C_READY_STATUS 0x2f0
63+
64+
#endif

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