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airliedairlied
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Merge tag 'drm-intel-gt-next-2025-07-02' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next
Driver Changes: Fixes/improvements/new stuff: - Avoid GuC scheduling stalls [guc] (Julia Filipchuk) - Remove force_probe requirement for DG1 (Ville Syrjälä) - Handle errors correctly to avoid losing GuC-2-Host messages [guc] (Jesus Narvaez) - Avoid double wakeref put if GuC context deregister failed [guc] (Jesus Narvaez) - Avoid timeline memory leak with signals and legacy platforms [ringbuf] (Janusz Krzysztofik) - Fix MEI (discrete) interrupt handler on RT kernels [gsc] (Junxiao Chang) Miscellaneous: - Allow larger memory allocation [selftest] (Mikolaj Wasiak) - Use provided dma_fence_is_chain (Tvrtko Ursulin) - Fix build error with GCOV and AutoFDO enabled [pmu] (Tzung-Bi Shih) - Fix build error some more (Arnd Bergmann) - Reduce stack usage in igt_vma_pin1() (Arnd Bergmann) - Move out engine related macros from i915_drv.h (Krzysztof Karas) - Move GEM_QUIRK_PIN_SWIZZLED_PAGES to i915_gem.h (Krzysztof Karas) Signed-off-by: Dave Airlie <[email protected]> From: Tvrtko Ursulin <[email protected]> Link: https://lore.kernel.org/r/aGTjUBeOQFw26bRT@linux
2 parents 7e28183 + dccf655 commit ca39a37

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12 files changed

+71
-77
lines changed

12 files changed

+71
-77
lines changed

‎drivers/gpu/drm/i915/gem/i915_gem_wait.c

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -106,11 +106,6 @@ static void fence_set_priority(struct dma_fence *fence,
106106
rcu_read_unlock();
107107
}
108108

109-
static inline bool __dma_fence_is_chain(const struct dma_fence *fence)
110-
{
111-
return fence->ops == &dma_fence_chain_ops;
112-
}
113-
114109
void i915_gem_fence_wait_priority(struct dma_fence *fence,
115110
const struct i915_sched_attr *attr)
116111
{
@@ -126,7 +121,7 @@ void i915_gem_fence_wait_priority(struct dma_fence *fence,
126121

127122
for (i = 0; i < array->num_fences; i++)
128123
fence_set_priority(array->fences[i], attr);
129-
} else if (__dma_fence_is_chain(fence)) {
124+
} else if (dma_fence_is_chain(fence)) {
130125
struct dma_fence *iter;
131126

132127
/* The chain is ordered; if we boost the last, we boost all */

‎drivers/gpu/drm/i915/gt/intel_engine.h

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -79,6 +79,29 @@ struct lock_class_key;
7979
#define ENGINE_WRITE(...) __ENGINE_WRITE_OP(write, __VA_ARGS__)
8080
#define ENGINE_WRITE_FW(...) __ENGINE_WRITE_OP(write_fw, __VA_ARGS__)
8181

82+
#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
83+
#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
84+
85+
#define __ENGINE_INSTANCES_MASK(mask, first, count) ({ \
86+
unsigned int first__ = (first); \
87+
unsigned int count__ = (count); \
88+
((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \
89+
})
90+
91+
#define ENGINE_INSTANCES_MASK(gt, first, count) \
92+
__ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count)
93+
94+
#define RCS_MASK(gt) \
95+
ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
96+
#define BCS_MASK(gt) \
97+
ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
98+
#define VDBOX_MASK(gt) \
99+
ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
100+
#define VEBOX_MASK(gt) \
101+
ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
102+
#define CCS_MASK(gt) \
103+
ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
104+
82105
#define GEN6_RING_FAULT_REG_READ(engine__) \
83106
intel_uncore_read((engine__)->uncore, RING_FAULT_REG(engine__))
84107

@@ -355,4 +378,12 @@ u64 intel_clamp_preempt_timeout_ms(struct intel_engine_cs *engine, u64 value);
355378
u64 intel_clamp_stop_timeout_ms(struct intel_engine_cs *engine, u64 value);
356379
u64 intel_clamp_timeslice_duration_ms(struct intel_engine_cs *engine, u64 value);
357380

381+
#define rb_to_uabi_engine(rb) \
382+
rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
383+
384+
#define for_each_uabi_engine(engine__, i915__) \
385+
for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
386+
(engine__); \
387+
(engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
388+
358389
#endif /* _INTEL_RINGBUFFER_H_ */

‎drivers/gpu/drm/i915/gt/intel_gsc.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -284,7 +284,7 @@ static void gsc_irq_handler(struct intel_gt *gt, unsigned int intf_id)
284284
if (gt->gsc.intf[intf_id].irq < 0)
285285
return;
286286

287-
ret = generic_handle_irq(gt->gsc.intf[intf_id].irq);
287+
ret = generic_handle_irq_safe(gt->gsc.intf[intf_id].irq);
288288
if (ret)
289289
gt_err_ratelimited(gt, "error handling GSC irq: %d\n", ret);
290290
}

‎drivers/gpu/drm/i915/gt/intel_ring_submission.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -610,7 +610,6 @@ static int ring_context_alloc(struct intel_context *ce)
610610
/* One ringbuffer to rule them all */
611611
GEM_BUG_ON(!engine->legacy.ring);
612612
ce->ring = engine->legacy.ring;
613-
ce->timeline = intel_timeline_get(engine->legacy.timeline);
614613

615614
GEM_BUG_ON(ce->state);
616615
if (engine->context_size) {
@@ -623,6 +622,8 @@ static int ring_context_alloc(struct intel_context *ce)
623622
ce->state = vma;
624623
}
625624

625+
ce->timeline = intel_timeline_get(engine->legacy.timeline);
626+
626627
return 0;
627628
}
628629

‎drivers/gpu/drm/i915/gt/uc/intel_guc.c

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -313,8 +313,13 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
313313
*
314314
* The same WA bit is used for both and 22011391025 is applicable to
315315
* all DG2.
316+
*
317+
* Platforms post DG2 prevent this issue in hardware by stalling
318+
* submissions. With this flag GuC will schedule as to avoid such
319+
* stalls.
316320
*/
317-
if (IS_DG2(gt->i915))
321+
if (IS_DG2(gt->i915) ||
322+
(CCS_MASK(gt) && GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)))
318323
flags |= GUC_WA_DUAL_QUEUE;
319324

320325
/* Wa_22011802037: graphics version 11/12 */

‎drivers/gpu/drm/i915/i915_drv.h

Lines changed: 0 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -66,8 +66,6 @@ struct intel_display;
6666
struct intel_pxp;
6767
struct vlv_s0ix_state;
6868

69-
#define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0)
70-
7169
/* Data Stolen Memory (DSM) aka "i915 stolen memory" */
7270
struct i915_dsm {
7371
/*
@@ -354,14 +352,6 @@ static inline struct intel_gt *to_gt(const struct drm_i915_private *i915)
354352
return i915->gt[0];
355353
}
356354

357-
#define rb_to_uabi_engine(rb) \
358-
rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
359-
360-
#define for_each_uabi_engine(engine__, i915__) \
361-
for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
362-
(engine__); \
363-
(engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
364-
365355
#define INTEL_INFO(i915) ((i915)->__info)
366356
#define RUNTIME_INFO(i915) (&(i915)->__runtime)
367357
#define DRIVER_CAPS(i915) (&(i915)->caps)
@@ -570,29 +560,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
570560
#define IS_GEN9_LP(i915) (IS_BROXTON(i915) || IS_GEMINILAKE(i915))
571561
#define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_GEN9_LP(i915))
572562

573-
#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
574-
#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
575-
576-
#define __ENGINE_INSTANCES_MASK(mask, first, count) ({ \
577-
unsigned int first__ = (first); \
578-
unsigned int count__ = (count); \
579-
((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \
580-
})
581-
582-
#define ENGINE_INSTANCES_MASK(gt, first, count) \
583-
__ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count)
584-
585-
#define RCS_MASK(gt) \
586-
ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
587-
#define BCS_MASK(gt) \
588-
ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
589-
#define VDBOX_MASK(gt) \
590-
ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
591-
#define VEBOX_MASK(gt) \
592-
ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
593-
#define CCS_MASK(gt) \
594-
ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
595-
596563
#define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode)
597564

598565
/*

‎drivers/gpu/drm/i915/i915_gem.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -134,4 +134,6 @@ int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
134134

135135
#define I915_GEM_IDLE_TIMEOUT (HZ / 5)
136136

137+
#define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0)
138+
137139
#endif /* __I915_GEM_H__ */

‎drivers/gpu/drm/i915/i915_pci.c

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -663,7 +663,6 @@ static const struct intel_device_info dg1_info = {
663663
DGFX_FEATURES,
664664
.__runtime.graphics.ip.rel = 10,
665665
PLATFORM(INTEL_DG1),
666-
.require_force_probe = 1,
667666
.platform_engine_mask =
668667
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
669668
BIT(VCS0) | BIT(VCS2),

‎drivers/gpu/drm/i915/i915_pmu.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -108,11 +108,11 @@ static unsigned int config_bit(const u64 config)
108108
return other_bit(config);
109109
}
110110

111-
static u32 config_mask(const u64 config)
111+
static __always_inline u32 config_mask(const u64 config)
112112
{
113113
unsigned int bit = config_bit(config);
114114

115-
if (__builtin_constant_p(config))
115+
if (__builtin_constant_p(bit))
116116
BUILD_BUG_ON(bit >
117117
BITS_PER_TYPE(typeof_member(struct i915_pmu,
118118
enable)) - 1);
@@ -121,7 +121,7 @@ static u32 config_mask(const u64 config)
121121
BITS_PER_TYPE(typeof_member(struct i915_pmu,
122122
enable)) - 1);
123123

124-
return BIT(config_bit(config));
124+
return BIT(bit);
125125
}
126126

127127
static bool is_engine_event(struct perf_event *event)

‎drivers/gpu/drm/i915/i915_vma.c

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1607,6 +1607,26 @@ int i915_vma_pin_ww(struct i915_vma *vma, struct i915_gem_ww_ctx *ww,
16071607
return err;
16081608
}
16091609

1610+
int i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
1611+
{
1612+
struct i915_gem_ww_ctx ww;
1613+
int err;
1614+
1615+
i915_gem_ww_ctx_init(&ww, true);
1616+
retry:
1617+
err = i915_gem_object_lock(vma->obj, &ww);
1618+
if (!err)
1619+
err = i915_vma_pin_ww(vma, &ww, size, alignment, flags);
1620+
if (err == -EDEADLK) {
1621+
err = i915_gem_ww_ctx_backoff(&ww);
1622+
if (!err)
1623+
goto retry;
1624+
}
1625+
i915_gem_ww_ctx_fini(&ww);
1626+
1627+
return err;
1628+
}
1629+
16101630
static void flush_idle_contexts(struct intel_gt *gt)
16111631
{
16121632
struct intel_engine_cs *engine;

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