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torvaldstorvalds
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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd: "A pile of Qualcomm clk driver fixes with two main themes: the alpha PLL driver and shared RCGs, and one fix for the Starfive JH7110 SoC. - The Alpha PLL clk_ops had multiple problems around setting rates. There are a handful of patches here that fix masks and skip enabling the clk from set_rate() when the PLL is disabled. The PLLs are crucial to operation of the system as almost all frequencies in the system are derived from them. - Parking shared RCGs at a slow always on clk at registration time breaks stuff. USB host mode can't handle such a slow frequency and the serial console gets all garbled when the UART clk is handed over to the kernel. There's a few patches that don't use the shared clk_ops for the UART clks and another one to skip parking the USB clk at registration time. - The Starfive PLL driver used for the CPU was busted causing cpufreq to fail because the clk didn't change to a safe parent during set_rate(). The fix is to register a notifier and switch to a safe parent so the PLL can change rate in a glitch free manner" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: qcom: gcc-sc8280xp: don't use parking clk_ops for QUPs clk: starfive: jh7110-sys: Add notifier for PLL0 clock clk: qcom: gcc-sm8650: Don't use shared clk_ops for QUPs clk: qcom: gcc-sm8550: Don't park the USB RCG at registration time clk: qcom: gcc-sm8550: Don't use parking clk_ops for QUPs clk: qcom: gcc-x1e80100: Don't use parking clk_ops for QUPs clk: qcom: ipq9574: Update the alpha PLL type for GPLLs clk: qcom: gcc-x1e80100: Fix USB 0 and 1 PHY GDSC pwrsts flags clk: qcom: clk-alpha-pll: Update set_rate for Zonda PLL clk: qcom: clk-alpha-pll: Fix zonda set_rate failure when PLL is disabled clk: qcom: clk-alpha-pll: Fix the trion pll postdiv set rate API clk: qcom: clk-alpha-pll: Fix the pll post div mask
2 parents 37d4cc6 + 71c03a8 commit d1f2d51

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10 files changed

+196
-115
lines changed

10 files changed

+196
-115
lines changed

‎drivers/clk/qcom/clk-alpha-pll.c‎

Lines changed: 22 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,8 @@
4040

4141
#define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
4242
# define PLL_POST_DIV_SHIFT 8
43-
# define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0)
43+
# define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0)
44+
# define PLL_ALPHA_MSB BIT(15)
4445
# define PLL_ALPHA_EN BIT(24)
4546
# define PLL_ALPHA_MODE BIT(25)
4647
# define PLL_VCO_SHIFT 20
@@ -1552,8 +1553,8 @@ clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
15521553
}
15531554

15541555
return regmap_update_bits(regmap, PLL_USER_CTL(pll),
1555-
PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1556-
val << PLL_POST_DIV_SHIFT);
1556+
PLL_POST_DIV_MASK(pll) << pll->post_div_shift,
1557+
val << pll->post_div_shift);
15571558
}
15581559

15591560
const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {
@@ -2117,6 +2118,18 @@ static void clk_zonda_pll_disable(struct clk_hw *hw)
21172118
regmap_write(regmap, PLL_OPMODE(pll), 0x0);
21182119
}
21192120

2121+
static void zonda_pll_adjust_l_val(unsigned long rate, unsigned long prate, u32 *l)
2122+
{
2123+
u64 remainder, quotient;
2124+
2125+
quotient = rate;
2126+
remainder = do_div(quotient, prate);
2127+
*l = quotient;
2128+
2129+
if ((remainder * 2) / prate)
2130+
*l = *l + 1;
2131+
}
2132+
21202133
static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
21212134
unsigned long prate)
21222135
{
@@ -2133,9 +2146,15 @@ static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
21332146
if (ret < 0)
21342147
return ret;
21352148

2149+
if (a & PLL_ALPHA_MSB)
2150+
zonda_pll_adjust_l_val(rate, prate, &l);
2151+
21362152
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
21372153
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
21382154

2155+
if (!clk_hw_is_enabled(hw))
2156+
return 0;
2157+
21392158
/* Wait before polling for the frequency latch */
21402159
udelay(5);
21412160

‎drivers/clk/qcom/clk-rcg.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -198,6 +198,7 @@ extern const struct clk_ops clk_byte2_ops;
198198
extern const struct clk_ops clk_pixel_ops;
199199
extern const struct clk_ops clk_gfx3d_ops;
200200
extern const struct clk_ops clk_rcg2_shared_ops;
201+
extern const struct clk_ops clk_rcg2_shared_no_init_park_ops;
201202
extern const struct clk_ops clk_dp_ops;
202203

203204
struct clk_rcg_dfs_data {

‎drivers/clk/qcom/clk-rcg2.c‎

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1348,6 +1348,36 @@ const struct clk_ops clk_rcg2_shared_ops = {
13481348
};
13491349
EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops);
13501350

1351+
static int clk_rcg2_shared_no_init_park(struct clk_hw *hw)
1352+
{
1353+
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1354+
1355+
/*
1356+
* Read the config register so that the parent is properly mapped at
1357+
* registration time.
1358+
*/
1359+
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &rcg->parked_cfg);
1360+
1361+
return 0;
1362+
}
1363+
1364+
/*
1365+
* Like clk_rcg2_shared_ops but skip the init so that the clk frequency is left
1366+
* unchanged at registration time.
1367+
*/
1368+
const struct clk_ops clk_rcg2_shared_no_init_park_ops = {
1369+
.init = clk_rcg2_shared_no_init_park,
1370+
.enable = clk_rcg2_shared_enable,
1371+
.disable = clk_rcg2_shared_disable,
1372+
.get_parent = clk_rcg2_shared_get_parent,
1373+
.set_parent = clk_rcg2_shared_set_parent,
1374+
.recalc_rate = clk_rcg2_shared_recalc_rate,
1375+
.determine_rate = clk_rcg2_determine_rate,
1376+
.set_rate = clk_rcg2_shared_set_rate,
1377+
.set_rate_and_parent = clk_rcg2_shared_set_rate_and_parent,
1378+
};
1379+
EXPORT_SYMBOL_GPL(clk_rcg2_shared_no_init_park_ops);
1380+
13511381
/* Common APIs to be used for DFS based RCGR */
13521382
static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l,
13531383
struct freq_tbl *f)

‎drivers/clk/qcom/gcc-ipq9574.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,7 @@ static const struct clk_parent_data gcc_sleep_clk_data[] = {
6868

6969
static struct clk_alpha_pll gpll0_main = {
7070
.offset = 0x20000,
71-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
71+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
7272
.clkr = {
7373
.enable_reg = 0x0b000,
7474
.enable_mask = BIT(0),
@@ -96,7 +96,7 @@ static struct clk_fixed_factor gpll0_out_main_div2 = {
9696

9797
static struct clk_alpha_pll_postdiv gpll0 = {
9898
.offset = 0x20000,
99-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
99+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
100100
.width = 4,
101101
.clkr.hw.init = &(const struct clk_init_data) {
102102
.name = "gpll0",
@@ -110,7 +110,7 @@ static struct clk_alpha_pll_postdiv gpll0 = {
110110

111111
static struct clk_alpha_pll gpll4_main = {
112112
.offset = 0x22000,
113-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
113+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
114114
.clkr = {
115115
.enable_reg = 0x0b000,
116116
.enable_mask = BIT(2),
@@ -125,7 +125,7 @@ static struct clk_alpha_pll gpll4_main = {
125125

126126
static struct clk_alpha_pll_postdiv gpll4 = {
127127
.offset = 0x22000,
128-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
128+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
129129
.width = 4,
130130
.clkr.hw.init = &(const struct clk_init_data) {
131131
.name = "gpll4",
@@ -139,7 +139,7 @@ static struct clk_alpha_pll_postdiv gpll4 = {
139139

140140
static struct clk_alpha_pll gpll2_main = {
141141
.offset = 0x21000,
142-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
142+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
143143
.clkr = {
144144
.enable_reg = 0x0b000,
145145
.enable_mask = BIT(1),
@@ -154,7 +154,7 @@ static struct clk_alpha_pll gpll2_main = {
154154

155155
static struct clk_alpha_pll_postdiv gpll2 = {
156156
.offset = 0x21000,
157-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
157+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
158158
.width = 4,
159159
.clkr.hw.init = &(const struct clk_init_data) {
160160
.name = "gpll2",

‎drivers/clk/qcom/gcc-sc8280xp.c‎

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1500,7 +1500,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
15001500
.parent_data = gcc_parent_data_0,
15011501
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
15021502
.flags = CLK_SET_RATE_PARENT,
1503-
.ops = &clk_rcg2_shared_ops,
1503+
.ops = &clk_rcg2_ops,
15041504
};
15051505

15061506
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
@@ -1517,7 +1517,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
15171517
.parent_data = gcc_parent_data_0,
15181518
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
15191519
.flags = CLK_SET_RATE_PARENT,
1520-
.ops = &clk_rcg2_shared_ops,
1520+
.ops = &clk_rcg2_ops,
15211521
};
15221522

15231523
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
@@ -1534,7 +1534,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
15341534
.parent_data = gcc_parent_data_0,
15351535
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
15361536
.flags = CLK_SET_RATE_PARENT,
1537-
.ops = &clk_rcg2_shared_ops,
1537+
.ops = &clk_rcg2_ops,
15381538
};
15391539

15401540
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
@@ -1551,7 +1551,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
15511551
.parent_data = gcc_parent_data_0,
15521552
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
15531553
.flags = CLK_SET_RATE_PARENT,
1554-
.ops = &clk_rcg2_shared_ops,
1554+
.ops = &clk_rcg2_ops,
15551555
};
15561556

15571557
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
@@ -1568,7 +1568,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
15681568
.parent_data = gcc_parent_data_0,
15691569
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
15701570
.flags = CLK_SET_RATE_PARENT,
1571-
.ops = &clk_rcg2_shared_ops,
1571+
.ops = &clk_rcg2_ops,
15721572
};
15731573

15741574
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
@@ -1585,7 +1585,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
15851585
.parent_data = gcc_parent_data_0,
15861586
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
15871587
.flags = CLK_SET_RATE_PARENT,
1588-
.ops = &clk_rcg2_shared_ops,
1588+
.ops = &clk_rcg2_ops,
15891589
};
15901590

15911591
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
@@ -1617,7 +1617,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
16171617
.parent_data = gcc_parent_data_0,
16181618
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
16191619
.flags = CLK_SET_RATE_PARENT,
1620-
.ops = &clk_rcg2_shared_ops,
1620+
.ops = &clk_rcg2_ops,
16211621
};
16221622

16231623
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
@@ -1634,7 +1634,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
16341634
.parent_data = gcc_parent_data_0,
16351635
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
16361636
.flags = CLK_SET_RATE_PARENT,
1637-
.ops = &clk_rcg2_shared_ops,
1637+
.ops = &clk_rcg2_ops,
16381638
};
16391639

16401640
static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
@@ -1651,7 +1651,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
16511651
.parent_data = gcc_parent_data_0,
16521652
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
16531653
.flags = CLK_SET_RATE_PARENT,
1654-
.ops = &clk_rcg2_shared_ops,
1654+
.ops = &clk_rcg2_ops,
16551655
};
16561656

16571657
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
@@ -1668,7 +1668,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
16681668
.parent_data = gcc_parent_data_0,
16691669
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
16701670
.flags = CLK_SET_RATE_PARENT,
1671-
.ops = &clk_rcg2_shared_ops,
1671+
.ops = &clk_rcg2_ops,
16721672
};
16731673

16741674
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
@@ -1685,7 +1685,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
16851685
.parent_data = gcc_parent_data_0,
16861686
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
16871687
.flags = CLK_SET_RATE_PARENT,
1688-
.ops = &clk_rcg2_shared_ops,
1688+
.ops = &clk_rcg2_ops,
16891689
};
16901690

16911691
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
@@ -1702,7 +1702,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
17021702
.parent_data = gcc_parent_data_0,
17031703
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
17041704
.flags = CLK_SET_RATE_PARENT,
1705-
.ops = &clk_rcg2_shared_ops,
1705+
.ops = &clk_rcg2_ops,
17061706
};
17071707

17081708
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
@@ -1719,7 +1719,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
17191719
.parent_data = gcc_parent_data_0,
17201720
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
17211721
.flags = CLK_SET_RATE_PARENT,
1722-
.ops = &clk_rcg2_shared_ops,
1722+
.ops = &clk_rcg2_ops,
17231723
};
17241724

17251725
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
@@ -1736,7 +1736,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
17361736
.parent_data = gcc_parent_data_0,
17371737
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
17381738
.flags = CLK_SET_RATE_PARENT,
1739-
.ops = &clk_rcg2_shared_ops,
1739+
.ops = &clk_rcg2_ops,
17401740
};
17411741

17421742
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
@@ -1753,7 +1753,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
17531753
.parent_data = gcc_parent_data_0,
17541754
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
17551755
.flags = CLK_SET_RATE_PARENT,
1756-
.ops = &clk_rcg2_shared_ops,
1756+
.ops = &clk_rcg2_ops,
17571757
};
17581758

17591759
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
@@ -1770,7 +1770,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
17701770
.parent_data = gcc_parent_data_0,
17711771
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
17721772
.flags = CLK_SET_RATE_PARENT,
1773-
.ops = &clk_rcg2_shared_ops,
1773+
.ops = &clk_rcg2_ops,
17741774
};
17751775

17761776
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
@@ -1787,7 +1787,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
17871787
.parent_data = gcc_parent_data_0,
17881788
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
17891789
.flags = CLK_SET_RATE_PARENT,
1790-
.ops = &clk_rcg2_shared_ops,
1790+
.ops = &clk_rcg2_ops,
17911791
};
17921792

17931793
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
@@ -1804,7 +1804,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
18041804
.parent_data = gcc_parent_data_0,
18051805
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
18061806
.flags = CLK_SET_RATE_PARENT,
1807-
.ops = &clk_rcg2_shared_ops,
1807+
.ops = &clk_rcg2_ops,
18081808
};
18091809

18101810
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
@@ -1821,7 +1821,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
18211821
.parent_data = gcc_parent_data_0,
18221822
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
18231823
.flags = CLK_SET_RATE_PARENT,
1824-
.ops = &clk_rcg2_shared_ops,
1824+
.ops = &clk_rcg2_ops,
18251825
};
18261826

18271827
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
@@ -1838,7 +1838,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
18381838
.parent_data = gcc_parent_data_0,
18391839
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
18401840
.flags = CLK_SET_RATE_PARENT,
1841-
.ops = &clk_rcg2_shared_ops,
1841+
.ops = &clk_rcg2_ops,
18421842
};
18431843

18441844
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
@@ -1855,7 +1855,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
18551855
.parent_data = gcc_parent_data_0,
18561856
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
18571857
.flags = CLK_SET_RATE_PARENT,
1858-
.ops = &clk_rcg2_shared_ops,
1858+
.ops = &clk_rcg2_ops,
18591859
};
18601860

18611861
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
@@ -1872,7 +1872,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
18721872
.parent_data = gcc_parent_data_0,
18731873
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
18741874
.flags = CLK_SET_RATE_PARENT,
1875-
.ops = &clk_rcg2_shared_ops,
1875+
.ops = &clk_rcg2_ops,
18761876
};
18771877

18781878
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
@@ -1889,7 +1889,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
18891889
.parent_data = gcc_parent_data_0,
18901890
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
18911891
.flags = CLK_SET_RATE_PARENT,
1892-
.ops = &clk_rcg2_shared_ops,
1892+
.ops = &clk_rcg2_ops,
18931893
};
18941894

18951895
static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
@@ -1906,7 +1906,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
19061906
.parent_data = gcc_parent_data_0,
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.num_parents = ARRAY_SIZE(gcc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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.ops = &clk_rcg2_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {

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