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drm/msm/dpu: remove DPU_CTL_SPLIT_DISPLAY from SAR2130P CTL blocks
Follow the changes in the commit a264995 ("drm/msm/dpu: remove DPU_CTL_SPLIT_DISPLAY from CTL blocks on DPU >= 5.0") and remove DPU_CTL_SPLIT_DISPLAY from the CTL blocks on the SAR2130P platform. Single CTL is used for all interfaces used by a single path Fixes: 1785751 ("drm/msm/dpu: add catalog entry for SAR2130P") Reviewed-by: Marijn Suijten <[email protected]> Reviewed-by: Jessica Zhang <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/651883/ Link: https://lore.kernel.org/r/20250506-dpu-sar2130p-no-split-display-v1-1-b619c0fddea5@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <[email protected]>
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drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -27,17 +27,16 @@ static const struct dpu_mdp_cfg sar2130p_mdp = {
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},
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};
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30-
/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
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static const struct dpu_ctl_cfg sar2130p_ctl[] = {
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{
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.name = "ctl_0", .id = CTL_0,
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.base = 0x15000, .len = 0x290,
35-
.features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
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.features = CTL_SM8550_MASK,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
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}, {
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.name = "ctl_1", .id = CTL_1,
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.base = 0x16000, .len = 0x290,
40-
.features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
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.features = CTL_SM8550_MASK,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
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}, {
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.name = "ctl_2", .id = CTL_2,

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