Skip to content

Commit e1f3f5b

Browse files
ujfalusivinodkoul
authored andcommitted
soundwire: intel: Add awareness of ACE3+ microphone privacy
ACE3 introduced microphone privacy and along this feature it adds a new register in vendor specific SHIM to control and status reporting. The control of mic privacy via the SHIM register is only to enable the interrupt generation via soundwire, but not handled by the soundwire code as the mic privacy is not a feature of the soundwire IP. On the other hand, printing the register value brings value for debugging, so add a new flag to allow this conditionally. Signed-off-by: Peter Ujfalusi <[email protected]> Reviewed-by: Ranjani Sridharan <[email protected]> Signed-off-by: Bard Liao <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
1 parent aab1202 commit e1f3f5b

File tree

4 files changed

+14
-0
lines changed

4 files changed

+14
-0
lines changed

drivers/soundwire/intel.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@ struct hdac_bus;
2222
* @shim_lock: mutex to handle access to shared SHIM registers
2323
* @shim_mask: global pointer to check SHIM register initialization
2424
* @clock_stop_quirks: mask defining requested behavior on pm_suspend
25+
* @mic_privacy: ACE version supports microphone privacy
2526
* @link_mask: global mask needed for power-up/down sequences
2627
* @cdns: Cadence master descriptor
2728
* @list: used to walk-through all masters exposed by the same controller
@@ -42,6 +43,7 @@ struct sdw_intel_link_res {
4243
struct mutex *shim_lock; /* protect shared registers */
4344
u32 *shim_mask;
4445
u32 clock_stop_quirks;
46+
bool mic_privacy;
4547
u32 link_mask;
4648
struct sdw_cdns *cdns;
4749
struct list_head list;

drivers/soundwire/intel_ace2x_debugfs.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -76,6 +76,12 @@ static int intel_reg_show(struct seq_file *s_file, void *data)
7676
ret += intel_sprintf(vs_s, false, buf, ret, SDW_SHIM2_INTEL_VS_IOCTL);
7777
ret += intel_sprintf(vs_s, false, buf, ret, SDW_SHIM2_INTEL_VS_ACTMCTL);
7878

79+
if (sdw->link_res->mic_privacy) {
80+
ret += scnprintf(buf + ret, RD_BUF - ret, "\nVS PVCCS\n");
81+
ret += intel_sprintf(vs_s, false, buf, ret,
82+
SDW_SHIM2_INTEL_VS_PVCCS);
83+
}
84+
7985
seq_printf(s_file, "%s", buf);
8086
kfree(buf);
8187

drivers/soundwire/intel_init.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -77,6 +77,7 @@ static struct sdw_intel_link_dev *intel_link_dev_register(struct sdw_intel_res *
7777
link->shim = res->mmio_base + SDW_SHIM2_GENERIC_BASE(link_id);
7878
link->shim_vs = res->mmio_base + SDW_SHIM2_VS_BASE(link_id);
7979
link->shim_lock = res->eml_lock;
80+
link->mic_privacy = res->mic_privacy;
8081
}
8182

8283
link->ops = res->ops;

include/linux/soundwire/sdw_intel.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -189,6 +189,9 @@
189189
#define SDW_SHIM3_INTEL_VS_ACTMCTL_DOAISE2 BIT(14)
190190
#define SDW_SHIM3_INTEL_VS_ACTMCTL_CLDE BIT(15)
191191

192+
/* ACE3+ Mic privacy control and status register */
193+
#define SDW_SHIM2_INTEL_VS_PVCCS 0x10
194+
192195
/**
193196
* struct sdw_intel_stream_params_data: configuration passed during
194197
* the @params_stream callback, e.g. for interaction with DSP
@@ -331,6 +334,7 @@ struct sdw_intel_ctx {
331334
* @shim_base: sdw shim base.
332335
* @alh_base: sdw alh base.
333336
* @ext: extended HDaudio link support
337+
* @mic_privacy: ACE version supports microphone privacy
334338
* @hbus: hdac_bus pointer, needed for power management
335339
* @eml_lock: mutex protecting shared registers in the HDaudio multi-link
336340
* space
@@ -349,6 +353,7 @@ struct sdw_intel_res {
349353
u32 shim_base;
350354
u32 alh_base;
351355
bool ext;
356+
bool mic_privacy;
352357
struct hdac_bus *hbus;
353358
struct mutex *eml_lock;
354359
};

0 commit comments

Comments
 (0)