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Merge tag 'mediatek-drm-next-20250515' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next
Mediatek DRM Next - 20250515 1. Prepare for support MT8195/88 HDMIv2 and DDCv2 2. DPI: Cleanups and add support for more formats 3. Cleanups and sanitization 4. Replace custom compare_dev with component_compare_of Signed-off-by: Dave Airlie <[email protected]> From: Chun-Kuang Hu <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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‎Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek HDMI MT8195 series HDMI Display Data Channel (DDC)
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maintainers:
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- AngeloGioacchino Del Regno <[email protected]>
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- CK Hu <[email protected]>
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properties:
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compatible:
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oneOf:
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- const: mediatek,mt8195-hdmi-ddc
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- items:
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- const: mediatek,mt8188-hdmi-ddc
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- const: mediatek,mt8195-hdmi-ddc
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clocks:
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maxItems: 1
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power-domains:
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maxItems: 1
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required:
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- compatible
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- clocks
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additionalProperties: false
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examples:
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- |
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hdmi {
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hdmi_ddc: i2c {
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compatible = "mediatek,mt8195-hdmi-ddc";
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clocks = <&clk26m>;
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};
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};
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...

‎Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek MT8195 series HDMI-TX Encoder
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maintainers:
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- AngeloGioacchino Del Regno <[email protected]>
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- CK Hu <[email protected]>
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description:
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The MediaTek HDMI-TX v2 encoder can generate HDMI format data based on
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the HDMI Specification 2.0b.
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properties:
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compatible:
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enum:
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- mediatek,mt8188-hdmi-tx
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- mediatek,mt8195-hdmi-tx
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: HDMI Peripheral Bus (APB) clock
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- description: HDCP and HDMI_TOP clock
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- description: HDCP, HDMI_TOP and HDMI Audio reference clock
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- description: VPP HDMI Split clock
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clock-names:
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items:
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- const: bus
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- const: hdcp
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- const: hdcp24m
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- const: hdmi-split
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i2c:
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type: object
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$ref: /schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml
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unevaluatedProperties: false
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description: HDMI DDC I2C controller
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phys:
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maxItems: 1
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description: PHY providing clocking TMDS and pixel to controller
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phy-names:
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items:
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- const: hdmi
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power-domains:
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maxItems: 1
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'#sound-dai-cells':
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const: 1
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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Input port, usually connected to the output port of a DPI
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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Output port that must be connected either to the input port of
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a HDMI connector node containing a ddc-i2c-bus, or to the input
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port of an attached bridge chip, such as a SlimPort transmitter.
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required:
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- port@0
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- port@1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- power-domains
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- phys
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- phy-names
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- ports
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allOf:
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- $ref: /schemas/sound/dai-common.yaml#
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt8195-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/mt8195-power.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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hdmi@1c300000 {
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compatible = "mediatek,mt8195-hdmi-tx";
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reg = <0 0x1c300000 0 0x1000>;
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clocks = <&topckgen CLK_TOP_HDMI_APB>,
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<&topckgen CLK_TOP_HDCP>,
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<&topckgen CLK_TOP_HDCP_24M>,
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<&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>;
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clock-names = "bus", "hdcp", "hdcp24m", "hdmi-split";
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interrupts = <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>;
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phys = <&hdmi_phy>;
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phy-names = "hdmi";
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power-domains = <&spm MT8195_POWER_DOMAIN_HDMI_TX>;
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pinctrl-names = "default";
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pinctrl-0 = <&hdmi_pins>;
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#sound-dai-cells = <1>;
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hdmitx_ddc: i2c {
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compatible = "mediatek,mt8195-hdmi-ddc";
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clocks = <&clk26m>;
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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hdmi_in: endpoint {
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remote-endpoint = <&dpi1_out>;
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};
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};
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port@1 {
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reg = <1>;
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hdmi_out: endpoint {
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remote-endpoint = <&hdmi_connector_in>;
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};
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};
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};
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};
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};

‎drivers/gpu/drm/mediatek/Makefile

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Original file line numberDiff line numberDiff line change
@@ -21,10 +21,8 @@ mediatek-drm-y := mtk_crtc.o \
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obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
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mediatek-drm-hdmi-objs := mtk_cec.o \
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mtk_hdmi.o \
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mtk_hdmi_ddc.o
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obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
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obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mtk_cec.o
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obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mtk_hdmi.o
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obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mtk_hdmi_ddc.o
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obj-$(CONFIG_DRM_MEDIATEK_DP) += mtk_dp.o

‎drivers/gpu/drm/mediatek/mtk_cec.c

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@@ -12,7 +12,6 @@
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#include <linux/platform_device.h>
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#include "mtk_cec.h"
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#include "mtk_hdmi.h"
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#include "mtk_drm_drv.h"
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#define TR_CONFIG 0x00
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cec->hpd_event = hpd_event;
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spin_unlock_irqrestore(&cec->lock, flags);
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}
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EXPORT_SYMBOL_NS_GPL(mtk_cec_set_hpd_event, "DRM_MTK_HDMI_V1");
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bool mtk_cec_hpd_high(struct device *dev)
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{
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return (status & (HDMI_PORD | HDMI_HTPLG)) == (HDMI_PORD | HDMI_HTPLG);
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}
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EXPORT_SYMBOL_NS_GPL(mtk_cec_hpd_high, "DRM_MTK_HDMI_V1");
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static void mtk_cec_htplg_irq_init(struct mtk_cec *cec)
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{
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.of_match_table = mtk_cec_of_ids,
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},
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};
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module_platform_driver(mtk_cec_driver);
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MODULE_DESCRIPTION("MediaTek HDMI CEC Driver");
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MODULE_LICENSE("GPL");

‎drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c

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@@ -492,11 +492,6 @@ static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
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{ /* sentinel */ }
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};
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static int compare_of(struct device *dev, void *data)
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{
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return dev->of_node == data;
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}
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static int ovl_adaptor_of_get_ddp_comp_type(struct device_node *node,
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enum mtk_ovl_adaptor_comp_type *ctype)
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{
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priv->ovl_adaptor_comp[id] = &comp_pdev->dev;
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drm_of_component_match_add(dev, match, compare_of, node);
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drm_of_component_match_add(dev, match, component_compare_of, node);
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dev_dbg(dev, "Adding component match for %pOF\n", node);
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}
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