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armurthysurajk8
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drm/i915/display: Acomodate format check in intel_plane_can_async_flip()
The function intel_plane_can_async_flip() checks for async supported modifier, add format support check also in the same function. Note: on ADL the surface base addr is required to be 16k aligned and if not might generate DMAR and GGTT faults leading to glitches. This patch changes the 16k alignment to 4k for planar formats. v11: Move filtering Indexed 8bit to a separate patch (Ville) v12: correct the commit msg and remove unwanted debug print (Ville) Signed-off-by: Arun R Murthy <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Suraj Kandpal <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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5 files changed

+14
-15
lines changed

5 files changed

+14
-15
lines changed

drivers/gpu/drm/i915/display/i9xx_plane.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -828,7 +828,7 @@ unsigned int vlv_plane_min_alignment(struct intel_plane *plane,
828828
{
829829
struct intel_display *display = to_intel_display(plane);
830830

831-
if (intel_plane_can_async_flip(plane, fb->modifier))
831+
if (intel_plane_can_async_flip(plane, fb->format->format, fb->modifier))
832832
return 256 * 1024;
833833

834834
/* FIXME undocumented so not sure what's actually needed */
@@ -852,7 +852,7 @@ static unsigned int g4x_primary_min_alignment(struct intel_plane *plane,
852852
{
853853
struct intel_display *display = to_intel_display(plane);
854854

855-
if (intel_plane_can_async_flip(plane, fb->modifier))
855+
if (intel_plane_can_async_flip(plane, fb->format->format, fb->modifier))
856856
return 256 * 1024;
857857

858858
if (intel_scanout_needs_vtd_wa(display))

drivers/gpu/drm/i915/display/intel_atomic_plane.c

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -174,8 +174,12 @@ bool intel_plane_needs_physical(struct intel_plane *plane)
174174
DISPLAY_INFO(display)->cursor_needs_physical;
175175
}
176176

177-
bool intel_plane_can_async_flip(struct intel_plane *plane, u64 modifier)
177+
bool intel_plane_can_async_flip(struct intel_plane *plane, u32 format,
178+
u64 modifier)
178179
{
180+
if (intel_format_info_is_yuv_semiplanar(drm_format_info(format), modifier))
181+
return false;
182+
179183
return plane->can_async_flip && plane->can_async_flip(modifier);
180184
}
181185

drivers/gpu/drm/i915/display/intel_atomic_plane.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,8 @@ enum plane_id;
2121

2222
struct intel_plane *
2323
intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id);
24-
bool intel_plane_can_async_flip(struct intel_plane *plane, u64 modifier);
24+
bool intel_plane_can_async_flip(struct intel_plane *plane, u32 format,
25+
u64 modifier);
2526
unsigned int intel_adjusted_rate(const struct drm_rect *src,
2627
const struct drm_rect *dst,
2728
unsigned int rate);

drivers/gpu/drm/i915/display/intel_display.c

Lines changed: 4 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -6021,22 +6021,16 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in
60216021
if (!plane->async_flip)
60226022
continue;
60236023

6024-
if (!intel_plane_can_async_flip(plane, new_plane_state->hw.fb->modifier)) {
6024+
if (!intel_plane_can_async_flip(plane, new_plane_state->hw.fb->format->format,
6025+
new_plane_state->hw.fb->modifier)) {
60256026
drm_dbg_kms(display->drm,
6026-
"[PLANE:%d:%s] Modifier 0x%llx does not support async flip\n",
6027+
"[PLANE:%d:%s] pixel format %p4cc / modifier 0x%llx does not support async flip\n",
60276028
plane->base.base.id, plane->base.name,
6029+
&new_plane_state->hw.fb->format->format,
60286030
new_plane_state->hw.fb->modifier);
60296031
return -EINVAL;
60306032
}
60316033

6032-
if (intel_format_info_is_yuv_semiplanar(new_plane_state->hw.fb->format,
6033-
new_plane_state->hw.fb->modifier)) {
6034-
drm_dbg_kms(display->drm,
6035-
"[PLANE:%d:%s] Planar formats do not support async flips\n",
6036-
plane->base.base.id, plane->base.name);
6037-
return -EINVAL;
6038-
}
6039-
60406034
/*
60416035
* We turn the first async flip request into a sync flip
60426036
* so that we can reconfigure the plane (eg. change modifier).

drivers/gpu/drm/i915/display/skl_universal_plane.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -601,7 +601,7 @@ static u32 tgl_plane_min_alignment(struct intel_plane *plane,
601601
* Figure out what's going on here...
602602
*/
603603
if (display->platform.alderlake_p &&
604-
intel_plane_can_async_flip(plane, fb->modifier))
604+
intel_plane_can_async_flip(plane, fb->format->format, fb->modifier))
605605
return mult * 16 * 1024;
606606

607607
switch (fb->modifier) {

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