Merge branches 'clk-bindings', 'clk-cleanup', 'clk-pwm', 'clk-hw-device', 'clk-xilinx' and 'clk-adi' into clk-next

 - Support atomic PWMs in the PWM clk driver
 - clk_hw_get_dev() and clk_hw_get_of_node() helpers

* clk-bindings: (30 commits)
  dt-bindings: clock: convert lpc1850-cgu.txt to yaml format
  dt-bindings: clock: Convert qca,ath79-pll to DT schema
  dt-bindings: clock: Convert nuvoton,npcm750-clk to DT schema
  dt-bindings: clock: Convert moxa,moxart-clock to DT schema
  dt-bindings: clock: Convert microchip,pic32mzda-clk to DT schema
  dt-bindings: clock: Convert maxim,max9485 to DT schema
  dt-bindings: clock: Convert qcom,krait-cc to DT schema
  dt-bindings: clock: qcom: Remove double colon from description
  dt-bindings: clock: convert lpc1850-ccu.txt to yaml format
  dt-bindings: clock: Convert alphascale,asm9260-clock-controller to DT schema
  dt-bindings: clock: Convert marvell,armada-370-corediv-clock to DT schema
  dt-bindings: clock: Convert marvell,armada-3700-periph-clock to DT schema
  dt-bindings: clock: Convert marvell,mvebu-core-clock to DT schema
  dt-bindings: clock: Convert marvell,berlin2-clk to DT schema
  dt-bindings: clock: Convert marvell,dove-divider-clock to DT schema
  dt-bindings: clock: Convert marvell,armada-3700-tbg-clock to DT schema
  dt-bindings: clock: Convert marvell-armada-370-gating-clock to DT schema
  dt-bindings: clock: Convert marvell,armada-xp-cpu-clock to DT schema
  dt-bindings: clock: Convert TI-NSPIRE clocks to DT schema
  dt-bindings: clock: Convert lsi,axm5516-clks to DT schema
  ...

* clk-cleanup: (29 commits)
  clk: clocking-wizard: Fix the round rate handling for versal
  clk: Fix typos
  clk: tegra: periph: Make tegra_clk_periph_ops static
  clk: tegra: periph: Fix error handling and resolve unsigned compare warning
  clk: imx: scu: convert from round_rate() to determine_rate()
  clk: imx: pllv4: convert from round_rate() to determine_rate()
  clk: imx: pllv3: convert from round_rate() to determine_rate()
  clk: imx: pllv2: convert from round_rate() to determine_rate()
  clk: imx: pll14xx: convert from round_rate() to determine_rate()
  clk: imx: pfd: convert from round_rate() to determine_rate()
  clk: imx: frac-pll: convert from round_rate() to determine_rate()
  clk: imx: fracn-gppll: convert from round_rate() to determine_rate()
  clk: imx: fixup-div: convert from round_rate() to determine_rate()
  clk: imx: cpu: convert from round_rate() to determine_rate()
  clk: imx: busy: convert from round_rate() to determine_rate()
  clk: imx: composite-93: remove round_rate() in favor of determine_rate()
  clk: imx: composite-8m: remove round_rate() in favor of determine_rate()
  clk: bcm: bcm2835: convert from round_rate() to determine_rate()
  MAINTAINERS: Include clk.py under COMMON CLK FRAMEWORK entry
  clk: ti: Simplify ti_find_clock_provider()
  ...

* clk-pwm:
  clk: pwm: Make use of non-sleeping PWMs
  clk: pwm: Don't reconfigure running PWM at probe time
  clk: pwm: Convert to use pwm_apply_might_sleep()
  clk: pwm: Let .get_duty_cycle() return the real duty cycle

* clk-hw-device:
  clk: tests: add clk_hw_get_dev() and clk_hw_get_of_node() tests
  clk: tests: Make clk_register_clk_parent_data_device_driver() common
  clk: add a clk_hw helpers to get the clock device or device_node

* clk-xilinx:
  clk: xilinx: vcu: Update vcu init/reset sequence
  clk: xilinx: vcu: unregister pll_post only if registered correctly

* clk-adi:
  clk: clk-axi-clkgen: fix coding style issues
  clk: clk-axi-clkgen move to min/max()
  clk: clk-axi-clkgen: detect axi_clkgen_limits at runtime
  include: adi-axi-common: add new helper macros
  include: linux: move adi-axi-common.h out of fpga
  clk: clk-axi-clkgen: make sure to include mod_devicetable.h
  clk: clk-axi-clkgen: fix fpfd_max frequency for zynq

Author: bebarino

Documentation/devicetree/bindings/clock/alphascale,acc.txt

@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/alphascale,asm9260-clock-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Alphascale Clock Controller
+
+maintainers:
+  - Oleksij Rempel <[email protected]>
+
+description: |
+  The ACC (Alphascale Clock Controller) is responsible for choosing proper
+  clock source, setting dividers and clock gates.
+
+  Simple one-cell clock specifier format is used, where the only cell is used
+  as an index of the clock inside the provider.
+  It is encouraged to use dt-binding for clock index definitions. SoC specific
+  dt-binding should be included to the device tree descriptor. For example
+  Alphascale ASM9260:
+
+  #include <dt-bindings/clock/alphascale,asm9260.h>
+
+  This binding contains two types of clock providers:
+
+    _AHB_ - AHB gate;
+    _SYS_ - adjustable clock source. Not all peripheral have _SYS_ clock provider.
+
+  All clock specific details can be found in the SoC documentation.
+
+properties:
+  compatible:
+    const: alphascale,asm9260-clock-controller
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+  clocks:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false

Documentation/devicetree/bindings/clock/alphascale,asm9260-clock-controller.yaml

@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/apm,xgene-device-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: APM X-Gene SoC device clocks
+
+maintainers:
+  - Khuong Dinh <[email protected]>
+
+properties:
+  compatible:
+    const: apm,xgene-device-clock
+
+  reg:
+    minItems: 1
+    maxItems: 2
+
+  reg-names:
+    items:
+      - enum: [ csr-reg, div-reg ]
+      - const: div-reg
+    minItems: 1
+
+  clocks:
+    maxItems: 1
+
+  "#clock-cells":
+    const: 1
+
+  clock-output-names:
+    maxItems: 1
+
+  clock-names:
+    maxItems: 1
+
+  csr-offset:
+    description: Offset to the CSR reset register
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0
+
+  csr-mask:
+    description: CSR reset mask bit
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0xf
+
+  enable-offset:
+    description: Offset to the enable register
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 8
+
+  enable-mask:
+    description: CSR enable mask bit
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0xf
+
+  divider-offset:
+    description: Offset to the divider register
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0
+
+  divider-width:
+    description: Width of the divider register
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0
+
+  divider-shift:
+    description: Bit shift of the divider register
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - '#clock-cells'
+  - clock-output-names
+
+additionalProperties: false

Documentation/devicetree/bindings/clock/apm,xgene-device-clock.yaml

@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/apm,xgene-socpll-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: APM X-Gene SoC PLL, PCPPLL, and PMD clocks
+
+maintainers:
+  - Khuong Dinh <[email protected]>
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - apm,xgene-pcppll-clock
+          - apm,xgene-pcppll-v2-clock
+          - apm,xgene-pmd-clock
+          - apm,xgene-socpll-clock
+          - apm,xgene-socpll-v2-clock
+
+  reg:
+    maxItems: 1
+
+  reg-names:
+    items:
+      - enum: [ csr-reg, div-reg ]
+      - const: div-reg
+    minItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    enum: [ pcppll, socpll ]
+
+  "#clock-cells":
+    const: 1
+
+  clock-output-names:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - '#clock-cells'
+  - clock-output-names
+
+additionalProperties: false