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Merge tag 'arm-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux into soc/newsoc
ARM Devicetrees for v6.17 Sophgo: Add support for Duo Module 01 Evaluation Board. This board uses SG2000(old codename CV181xH), which is dual-arch, RISC-V and ARM64. This patch add the support for ARM64. Signed-off-by: Chen Wang <[email protected]> * tag 'arm-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux: arm64: defconfig: Enable rudimentary Sophgo SG2000 support arm64: Add SOPHGO SOC family Kconfig support arm64: dts: sophgo: Add Duo Module 01 Evaluation Board arm64: dts: sophgo: Add Duo Module 01 arm64: dts: sophgo: Add initial SG2000 SoC device tree Link: https://lore.kernel.org/r/MAUPR01MB11072C4B088AAC02268044E95FE5FA@MAUPR01MB11072.INDPRD01.PROD.OUTLOOK.COM Signed-off-by: Arnd Bergmann <[email protected]>
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‎arch/arm64/Kconfig.platforms

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@@ -327,6 +327,12 @@ config ARCH_INTEL_SOCFPGA
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Stratix 10 (ex. Altera), Stratix10 Software Virtual Platform,
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Agilex and eASIC N5X.
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config ARCH_SOPHGO
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bool "Sophgo SoCs"
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select ARCH_HAS_RESET_CONTROLLER
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help
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This enables support for Sophgo SoC platform hardware.
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config ARCH_STM32
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bool "STMicroelectronics STM32 SoC Family"
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select GPIOLIB

‎arch/arm64/boot/dts/Makefile

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@@ -30,6 +30,7 @@ subdir-y += realtek
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subdir-y += renesas
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subdir-y += rockchip
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subdir-y += socionext
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subdir-y += sophgo
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subdir-y += sprd
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subdir-y += st
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subdir-y += synaptics

‎arch/arm64/boot/dts/sophgo/Makefile

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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_SOPHGO) += sg2000-milkv-duo-module-01-evb.dtb

‎arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01-evb.dts

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/dts-v1/;
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#include "sg2000-milkv-duo-module-01.dtsi"
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/ {
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model = "Milk-V Duo Module 01 Evaluation Board";
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compatible = "milkv,duo-module-01-evb", "milkv,duo-module-01", "sophgo,sg2000";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&pinctrl {
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sdhci0_cfg: sdhci0-cfg {
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sdhci0-cd-pins {
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pinmux = <PINMUX(PIN_SD0_CD, 0)>;
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bias-pull-up;
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drive-strength-microamp = <10800>;
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power-source = <3300>;
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};
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sdhci0-clk-pins {
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pinmux = <PINMUX(PIN_SD0_CLK, 0)>;
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bias-pull-up;
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drive-strength-microamp = <16100>;
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power-source = <3300>;
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};
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sdhci0-cmd-pins {
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pinmux = <PINMUX(PIN_SD0_CMD, 0)>;
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bias-pull-up;
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drive-strength-microamp = <10800>;
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power-source = <3300>;
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};
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sdhci0-data-pins {
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pinmux = <PINMUX(PIN_SD0_D0, 0)>,
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<PINMUX(PIN_SD0_D1, 0)>,
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<PINMUX(PIN_SD0_D2, 0)>,
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<PINMUX(PIN_SD0_D3, 0)>;
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bias-pull-up;
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drive-strength-microamp = <10800>;
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power-source = <3300>;
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};
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};
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uart0_cfg: uart0-cfg {
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uart0-pins {
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pinmux = <PINMUX(PIN_UART0_TX, 0)>,
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<PINMUX(PIN_UART0_RX, 0)>;
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bias-pull-up;
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drive-strength-microamp = <10800>;
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power-source = <3300>;
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};
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};
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};
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&uart0 {
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pinctrl-0 = <&uart0_cfg>;
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pinctrl-names = "default";
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status = "okay";
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};
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&sdhci0 {
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bus-width = <4>;
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no-1-8-v;
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no-mmc;
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no-sdio;
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disable-wp;
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pinctrl-0 = <&sdhci0_cfg>;
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pinctrl-names = "default";
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status = "okay";
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};

‎arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01.dtsi

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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#include <dt-bindings/pinctrl/pinctrl-sg2000.h>
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#include "sg2000.dtsi"
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/ {
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model = "Milk-V Duo Module 01";
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compatible = "milkv,duo-module-01", "sophgo,sg2000";
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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};
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};
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&osc {
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clock-frequency = <25000000>;
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};
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&emmc {
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bus-width = <4>;
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no-1-8-v;
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cap-mmc-hw-reset;
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no-sd;
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no-sdio;
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non-removable;
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status = "okay";
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};
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/* Wi-Fi */
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&sdhci1 {
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bus-width = <4>;
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cap-sdio-irq;
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no-mmc;
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no-sd;
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non-removable;
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};

‎arch/arm64/boot/dts/sophgo/sg2000.dtsi

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI (nr)
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <riscv/sophgo/cv180x.dtsi>
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#include <riscv/sophgo/cv181x.dtsi>
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/ {
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compatible = "sophgo,sg2000";
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0>;
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enable-method = "psci";
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i-cache-size = <32768>;
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d-cache-size = <32768>;
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next-level-cache = <&l2>;
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};
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l2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x20000>;
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x20000000>; /* 512MiB */
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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cpu_on = <0xc4000003>;
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cpu_off = <0x84000002>;
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};
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soc {
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gic: interrupt-controller@1f01000 {
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compatible = "arm,cortex-a15-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x01f01000 0x1000>,
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<0x01f02000 0x2000>;
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};
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pinctrl: pinctrl@3001000 {
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compatible = "sophgo,sg2000-pinctrl";
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reg = <0x03001000 0x1000>,
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<0x05027000 0x1000>;
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reg-names = "sys", "rtc";
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};
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clk: clock-controller@3002000 {
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compatible = "sophgo,sg2000-clk";
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reg = <0x03002000 0x1000>;
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clocks = <&osc>;
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#clock-cells = <1>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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always-on;
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clock-frequency = <25000000>;
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};
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};

‎arch/arm64/configs/defconfig

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@@ -68,6 +68,7 @@ CONFIG_ARCH_RENESAS=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_ARCH_SEATTLE=y
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CONFIG_ARCH_INTEL_SOCFPGA=y
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CONFIG_ARCH_SOPHGO=y
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CONFIG_ARCH_STM32=y
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CONFIG_ARCH_SYNQUACER=y
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CONFIG_ARCH_TEGRA=y
@@ -656,6 +657,7 @@ CONFIG_PINCTRL_SM8450_LPASS_LPI=m
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CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m
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CONFIG_PINCTRL_SM8550_LPASS_LPI=m
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CONFIG_PINCTRL_SM8650_LPASS_LPI=m
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CONFIG_PINCTRL_SOPHGO_SG2000=y
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CONFIG_GPIO_ALTERA=m
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CONFIG_GPIO_DAVINCI=y
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CONFIG_GPIO_DWAPB=y
@@ -1432,6 +1434,7 @@ CONFIG_QCOM_HFPLL=y
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CONFIG_CLK_GFM_LPASS_SM8250=m
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CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y
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CONFIG_CLK_RENESAS_VBATTB=m
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CONFIG_CLK_SOPHGO_CV1800=y
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CONFIG_HWSPINLOCK=y
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CONFIG_HWSPINLOCK_OMAP=m
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CONFIG_HWSPINLOCK_QCOM=y
@@ -1533,6 +1536,7 @@ CONFIG_QCOM_SPMI_VADC=m
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CONFIG_QCOM_SPMI_ADC5=m
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CONFIG_ROCKCHIP_SARADC=m
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CONFIG_RZG2L_ADC=m
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CONFIG_SOPHGO_CV1800B_ADC=m
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CONFIG_TI_ADS1015=m
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CONFIG_TI_AM335X_ADC=m
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CONFIG_IIO_CROS_EC_SENSORS_CORE=m

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