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Merge tag 'riscv-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux into soc/dt
RISC-V Devicetrees for v6.17 Sophgo: For CV18xx serials: There are three major changes. The first is to add the RTCSYS MFD node, which provides rich control registers for soc power management and other rich control functions; the second is to add the reset controller node and add related reset properties for other peripherals; the third is to add ethernet controller related nodes to the soc and enable ethernet device control for HuashanPi. For SG2042: There are three major changes. The first is to add ISA extensions such as xtheadvector/ziccrse/zfh for cpu cores; the second is add ethernet controller support; the third is add two new boards EVB_V1 & EVB_V2 which use SG2042 SoC. For SG2044: There are many changes. The first is to add pmu configuration; the second is to add ISA extensions ziccrse and add missing riscv,cbop-block-size property for cpu cores; the third is to add more peripherals nodes for SoC after clock controller is ready, such as MSI/PCIe/pwm/SPI-NOR etc. This PR also add HWMON MCU device for the sophgo-srd3-10 board and reserve uart0 node for sophgo-srd3-10 board because uart0 is already occupied by the firmware. This PR also moves sophgo.yaml from the riscv directory to soc/sophgo for sharing between riscv and arm. CV18xx SoC contains a RISC-V big core and an ARM64 big core. Moving sophgo.yaml to a shared location will help us add support for ARM cores to the CV18xx chip in the future. Signed-off-by: Chen Wang <[email protected]> * tag 'riscv-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux: (32 commits) riscv: dts: sophgo: fix mdio node name for CV180X riscv: dts: sophgo: sophgo-srd3-10: reserve uart0 device riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings riscv: dts: sophgo: add ethernet GMAC device for sg2042 riscv: dts: sophgo: Enable ethernet device for Huashan Pi riscv: dts: sophgo: Add mdio multiplexer device for cv18xx riscv: dts: sophgo: Add ethernet device for cv18xx riscv: dts: sophgo: sg2044: add pmu configuration riscv: dts: sophgo: sg2044: add ziccrse extension riscv: dts: sophgo: add zfh for sg2042 riscv: dts: sophgo: add ziccrse for sg2042 riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree riscv: dts: sophgo: sg2044: add PCIe device support for SG2044 riscv: dts: sophgo: sg2044: add MSI device support for SG2044 riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000 riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property ... Link: https://lore.kernel.org/r/MAUPR01MB1107297124C9DA0CD77DA3DC1FE5FA@MAUPR01MB11072.INDPRD01.PROD.OUTLOOK.COM Signed-off-by: Arnd Bergmann <[email protected]>
2 parents cd7dace + 7f90573 commit 11949d2

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‎Documentation/devicetree/bindings/riscv/sophgo.yaml renamed to ‎Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
22
%YAML 1.2
33
---
4-
$id: http://devicetree.org/schemas/riscv/sophgo.yaml#
4+
$id: http://devicetree.org/schemas/soc/sophgo/sophgo.yaml#
55
$schema: http://devicetree.org/meta-schemas/core.yaml#
66

77
title: Sophgo SoC-based boards
@@ -26,6 +26,11 @@ properties:
2626
- enum:
2727
- sophgo,huashan-pi
2828
- const: sophgo,cv1812h
29+
- items:
30+
- enum:
31+
- milkv,duo-module-01-evb
32+
- const: milkv,duo-module-01
33+
- const: sophgo,sg2000
2934
- items:
3035
- enum:
3136
- sipeed,licheerv-nano-b
@@ -34,6 +39,8 @@ properties:
3439
- items:
3540
- enum:
3641
- milkv,pioneer
42+
- sophgo,sg2042-evb-v1
43+
- sophgo,sg2042-evb-v2
3744
- const: sophgo,sg2042
3845
- items:
3946
- enum:

‎arch/riscv/boot/dts/sophgo/Makefile

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,4 +3,6 @@ dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
33
dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
44
dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano-b.dtb
55
dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
6+
dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v1.dtb
7+
dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v2.dtb
68
dtb-$(CONFIG_ARCH_SOPHGO) += sg2044-sophgo-srd3-10.dtb

‎arch/riscv/boot/dts/sophgo/cv180x.dtsi

Lines changed: 110 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@
77
#include <dt-bindings/clock/sophgo,cv1800.h>
88
#include <dt-bindings/gpio/gpio.h>
99
#include <dt-bindings/interrupt-controller/irq.h>
10+
#include "cv18xx-reset.h"
1011

1112
/ {
1213
#address-cells = <1>;
@@ -24,11 +25,45 @@
2425
#size-cells = <1>;
2526
ranges;
2627

28+
rst: reset-controller@3003000 {
29+
compatible = "sophgo,cv1800b-reset";
30+
reg = <0x3003000 0x1000>;
31+
#reset-cells = <1>;
32+
};
33+
34+
mdio: mdio-mux@3009800 {
35+
compatible = "mdio-mux-mmioreg", "mdio-mux";
36+
reg = <0x3009800 0x4>;
37+
#address-cells = <1>;
38+
#size-cells = <0>;
39+
mdio-parent-bus = <&gmac0_mdio>;
40+
mux-mask = <0x80>;
41+
status = "disabled";
42+
43+
internal_mdio: mdio@0 {
44+
#address-cells = <1>;
45+
#size-cells = <0>;
46+
reg = <0>;
47+
48+
internal_ephy: phy@0 {
49+
compatible = "ethernet-phy-ieee802.3-c22";
50+
reg = <1>;
51+
};
52+
};
53+
54+
external_mdio: mdio@80 {
55+
#address-cells = <1>;
56+
#size-cells = <0>;
57+
reg = <0x80>;
58+
};
59+
};
60+
2761
gpio0: gpio@3020000 {
2862
compatible = "snps,dw-apb-gpio";
2963
reg = <0x3020000 0x1000>;
3064
#address-cells = <1>;
3165
#size-cells = <0>;
66+
resets = <&rst RST_GPIO0>;
3267

3368
porta: gpio-controller@0 {
3469
compatible = "snps,dw-apb-gpio-port";
@@ -47,6 +82,7 @@
4782
reg = <0x3021000 0x1000>;
4883
#address-cells = <1>;
4984
#size-cells = <0>;
85+
resets = <&rst RST_GPIO1>;
5086

5187
portb: gpio-controller@0 {
5288
compatible = "snps,dw-apb-gpio-port";
@@ -65,6 +101,7 @@
65101
reg = <0x3022000 0x1000>;
66102
#address-cells = <1>;
67103
#size-cells = <0>;
104+
resets = <&rst RST_GPIO2>;
68105

69106
portc: gpio-controller@0 {
70107
compatible = "snps,dw-apb-gpio-port";
@@ -83,6 +120,7 @@
83120
reg = <0x3023000 0x1000>;
84121
#address-cells = <1>;
85122
#size-cells = <0>;
123+
resets = <&rst RST_GPIO3>;
86124

87125
portd: gpio-controller@0 {
88126
compatible = "snps,dw-apb-gpio-port";
@@ -126,6 +164,7 @@
126164
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
127165
clock-names = "ref", "pclk";
128166
interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>;
167+
resets = <&rst RST_I2C0>;
129168
status = "disabled";
130169
};
131170

@@ -137,6 +176,7 @@
137176
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
138177
clock-names = "ref", "pclk";
139178
interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>;
179+
resets = <&rst RST_I2C1>;
140180
status = "disabled";
141181
};
142182

@@ -148,6 +188,7 @@
148188
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
149189
clock-names = "ref", "pclk";
150190
interrupts = <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_LEVEL_HIGH>;
191+
resets = <&rst RST_I2C2>;
151192
status = "disabled";
152193
};
153194

@@ -159,6 +200,7 @@
159200
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
160201
clock-names = "ref", "pclk";
161202
interrupts = <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_LEVEL_HIGH>;
203+
resets = <&rst RST_I2C3>;
162204
status = "disabled";
163205
};
164206

@@ -170,9 +212,56 @@
170212
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
171213
clock-names = "ref", "pclk";
172214
interrupts = <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_LEVEL_HIGH>;
215+
resets = <&rst RST_I2C4>;
173216
status = "disabled";
174217
};
175218

219+
gmac0: ethernet@4070000 {
220+
compatible = "sophgo,cv1800b-dwmac", "snps,dwmac-3.70a";
221+
reg = <0x04070000 0x10000>;
222+
clocks = <&clk CLK_AXI4_ETH0>, <&clk CLK_ETH0_500M>;
223+
clock-names = "stmmaceth", "ptp_ref";
224+
interrupts = <SOC_PERIPHERAL_IRQ(15) IRQ_TYPE_LEVEL_HIGH>;
225+
interrupt-names = "macirq";
226+
phy-handle = <&internal_ephy>;
227+
phy-mode = "internal";
228+
resets = <&rst RST_ETH0>;
229+
reset-names = "stmmaceth";
230+
rx-fifo-depth = <8192>;
231+
tx-fifo-depth = <8192>;
232+
snps,multicast-filter-bins = <0>;
233+
snps,perfect-filter-entries = <1>;
234+
snps,aal;
235+
snps,txpbl = <8>;
236+
snps,rxpbl = <8>;
237+
snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
238+
snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
239+
snps,axi-config = <&gmac0_stmmac_axi_setup>;
240+
status = "disabled";
241+
242+
gmac0_mdio: mdio {
243+
compatible = "snps,dwmac-mdio";
244+
#address-cells = <1>;
245+
#size-cells = <0>;
246+
};
247+
248+
gmac0_mtl_rx_setup: rx-queues-config {
249+
snps,rx-queues-to-use = <1>;
250+
queue0 {};
251+
};
252+
253+
gmac0_mtl_tx_setup: tx-queues-config {
254+
snps,tx-queues-to-use = <1>;
255+
queue0 {};
256+
};
257+
258+
gmac0_stmmac_axi_setup: stmmac-axi-config {
259+
snps,blen = <16 8 4 0 0 0 0>;
260+
snps,rd_osr_lmt = <2>;
261+
snps,wr_osr_lmt = <1>;
262+
};
263+
};
264+
176265
uart0: serial@4140000 {
177266
compatible = "snps,dw-apb-uart";
178267
reg = <0x04140000 0x100>;
@@ -181,6 +270,7 @@
181270
clock-names = "baudclk", "apb_pclk";
182271
reg-shift = <2>;
183272
reg-io-width = <4>;
273+
resets = <&rst RST_UART0>;
184274
status = "disabled";
185275
};
186276

@@ -192,6 +282,7 @@
192282
clock-names = "baudclk", "apb_pclk";
193283
reg-shift = <2>;
194284
reg-io-width = <4>;
285+
resets = <&rst RST_UART1>;
195286
status = "disabled";
196287
};
197288

@@ -203,6 +294,7 @@
203294
clock-names = "baudclk", "apb_pclk";
204295
reg-shift = <2>;
205296
reg-io-width = <4>;
297+
resets = <&rst RST_UART2>;
206298
status = "disabled";
207299
};
208300

@@ -214,6 +306,7 @@
214306
clock-names = "baudclk", "apb_pclk";
215307
reg-shift = <2>;
216308
reg-io-width = <4>;
309+
resets = <&rst RST_UART3>;
217310
status = "disabled";
218311
};
219312

@@ -225,6 +318,7 @@
225318
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
226319
clock-names = "ssi_clk", "pclk";
227320
interrupts = <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_LEVEL_HIGH>;
321+
resets = <&rst RST_SPI0>;
228322
status = "disabled";
229323
};
230324

@@ -236,6 +330,7 @@
236330
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
237331
clock-names = "ssi_clk", "pclk";
238332
interrupts = <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_LEVEL_HIGH>;
333+
resets = <&rst RST_SPI1>;
239334
status = "disabled";
240335
};
241336

@@ -247,6 +342,7 @@
247342
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
248343
clock-names = "ssi_clk", "pclk";
249344
interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>;
345+
resets = <&rst RST_SPI2>;
250346
status = "disabled";
251347
};
252348

@@ -258,6 +354,7 @@
258354
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
259355
clock-names = "ssi_clk", "pclk";
260356
interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>;
357+
resets = <&rst RST_SPI3>;
261358
status = "disabled";
262359
};
263360

@@ -269,6 +366,7 @@
269366
clock-names = "baudclk", "apb_pclk";
270367
reg-shift = <2>;
271368
reg-io-width = <4>;
369+
resets = <&rst RST_UART4>;
272370
status = "disabled";
273371
};
274372

@@ -307,5 +405,17 @@
307405
snps,data-width = <2>;
308406
status = "disabled";
309407
};
408+
409+
rtc@5025000 {
410+
compatible = "sophgo,cv1800b-rtc", "syscon";
411+
reg = <0x5025000 0x2000>;
412+
interrupts = <SOC_PERIPHERAL_IRQ(1) IRQ_TYPE_LEVEL_HIGH>,
413+
<SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>,
414+
<SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>;
415+
interrupt-names = "alarm", "longpress", "vbat";
416+
clocks = <&clk CLK_RTC_25M>,
417+
<&clk CLK_SRC_RTC_SYS_0>;
418+
clock-names = "rtc", "mcu";
419+
};
310420
};
311421
};

‎arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -55,6 +55,14 @@
5555
non-removable;
5656
};
5757

58+
&gmac0 {
59+
status = "okay";
60+
};
61+
62+
&mdio {
63+
status = "okay";
64+
};
65+
5866
&sdhci0 {
5967
status = "okay";
6068
bus-width = <4>;

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